EP0149799A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1984-12-14
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Granted: —
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Expires: 2004-12-14
Abstract
Abstract Disclosed is a semiconductor memory device which has a transfer transistor (33a) of a MOS structure on a surface of a semiconductor body (21, 22), and a trenched capacitor (25a) having a groove (26a) which is formed so as to extend from a surface of the semiconductor body to a certain depth thereof and an electrode (28a) which is formed from a bottom portion of the groove to at least a level above an opening of the groove, the source region (34a) of the transfer transistor (33a) being connected to the electrode (29a) of the trenched capacitor (25a) and the drain region (35a) thereof being connected to a bit line (41).
Inventors
- 👤 Yukimasa C/O Patent Division Uchida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 20:16
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
153 words
A semiconductor memory device comprising: a transfer transistor having source and drain regions (34a, 35a) which are formed in a surface of a semiconductor body (21, 22) so as to be electrically isolated from each other and a gate electrode (37a) which is formed on a portion of said semiconductor body between said source and drain regions; and a trenched capacitor (25a) having a groove (26a) which is formed so as to extend from the surface of said semiconductor body to a predetermined depth thereof and an electrode (28a) which is formed from a bottom portion of said groove to at least a level above an opening of said groove through a capacitor insulation film (29a), characterized in that one of said source and drain regions (34a, 35a) is connected to said electrode of said trenched capacitor and the other of said source and drain regions is connected to a bit line (41).
Claim 2
Dependent Claim
153 words
A semiconductor memory device comprising: a transfer transistor having source and drain regions (34a, 35a) which are formed in a surface of a semiconductor body (21, 22) so as to be electrically isolated from each other and a gate electrode (37a) which is formed on a portion of said semiconductor body between said source and drain regions; and a trenched capacitor (25a) having a groove (26a) which is formed so as to extend from the surface of said semiconductor body to a predetermined depth thereof and an electrode (28a) which is formed from a bottom portion of said groove to at least a level above an opening of said groove through a capacitor insulation film (29a), characterized in that one of said source and drain regions (34a, 35a) is connected to said electrode of said trenched capacitor and the other of said source and drain regions is connected to a bit line (41).
Claim 3
Dependent Claim
113 words
A semiconductor memory device according to claim 1, characterized in that said semiconductor body (21, 22) comprises a semiconductor substrate (21) of a second conductivity type (n) on which a semiconductor layer (22) of a first conductivity type (p) is formed; said transfer transistor (33a) is formed on a surface of said semiconductor layer; said groove (26a) of said trenched capacitor is formed so as to extend from the surface of said semiconductor layer to the predetermined depth of said semiconductor substrate through said semiconductor layer; and an impurity diffusion region (27a) of the second conductivity type is formed on portions of said semiconductor layer and said semiconductor substrate which define said groove.
Claim 4
Dependent Claim
41 words
A semiconductor memory device according to claim 2, characterized in that said semiconductor layer (22) of the first conductivity type is a well region (22) which is selectively formed on the surface of said semiconductor substrate of the second conductivity type.
Claim 5
Dependent Claim
117 words
A semiconductor memory device according to claim 1, characterized in that said semiconductor body (21, 22, 44) comprises a semiconductor substrate (21) of a first conductivity type, a semiconductor layer (22) of the first conductivity type formed on said semiconductor substrate, and a buried layer (44) of a second conductivity type formed at an interface between said semiconductor substrate and said semiconductor layer; said groove (26a) of said trenched capacitor is formed so as to extend from the surface of said semiconductor layer to a position inside said buried layer; and an impurity diffusion region (27a) of the second conductivity type is formed on portions of said semiconductor layer and said buried layer which define said groove.
References Cited (Backward Citations)
No citation records indexed.
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