US5227995A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density semiconductor memory module using split finger lead frame
Assignee: International Business Machines Corp
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Filing: 1990-07-17
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Granted: 1993-07-13
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Expires: 2010-07-17
Abstract
Abstract The semiconductor memory module comprises a housing of plastic or ceramic in which two chips are stacked together back-to-back. The pads of the chips are electrically connected by wire bonding to beam leads which comprise outer bond leads, generally arranged outside the housing to form the contact pins or contact leads of the module to a printed circuit board, and inner bond leads in the housing. The inner bond leads are split and spread in the area of the inner lead bond ends into upper and lower sets forming a gap for receiving and holding the stacked chips.
Inventors
- 👤 Erich Klink
- 👤 Helmut Kohler
- 👤 Harald Pross
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:09
CPC Classifications
H; H10; H10W; H10W90/00; H10W90/701; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W70/421; H10W70/424; H10W70/427; H10W70/429; H10W90/811; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/851; H10W72/853; H10W72/865; H10W74/00; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
234 words
A method for forming high density semiconductor modules comprising the following steps: selecting a pair of semiconductor chips having major active surfaces and parallel major inactive surfaces, said major active surfaces having device input and output pads thereon, joining the major inactive surfaces of said chips back-to-back to form a stack having the major active surfaces and the pads thereon facing outwards from said stack, forming a lead frame with a spaced series of leads having inner ends and outer ends, splitting the inner ends of the leads to form split inner ends, forming the split inner ends of the leads into divergent upper and lower sets with a space therebetween, inserting said stack into the space between the sets so that the major active surface of each chip in said stack is adjacent to a respective one of said sets, joining said inner ends to said adjacent major active surface with an insulative adhesive, connecting the pads on one of said chips in said stack to said upper set of ends and the pads on the other of said chips in said stack to the lower set of ends with bonding wires to form a wire bonded chip stack, encapsulating said wire bonded chip stack with encapsulating so selected ones of leads have their outer ends extending out of said encapsulation, forming the outer ends of said leads extending out of said encapsulation.
Claim 2
Independent Claim
234 words
A method for forming high density semiconductor modules comprising the following steps: selecting a pair of semiconductor chips having major active surfaces and parallel major inactive surfaces, said major active surfaces having device input and output pads thereon, joining the major inactive surfaces of said chips back-to-back to form a stack having the major active surfaces and the pads thereon facing outwards from said stack, forming a lead frame with a spaced series of leads having inner ends and outer ends, splitting the inner ends of the leads to form split inner ends, forming the split inner ends of the leads into divergent upper and lower sets with a space therebetween, inserting said stack into the space between the sets so that the major active surface of each chip in said stack is adjacent to a respective one of said sets, joining said inner ends to said adjacent major active surface with an insulative adhesive, connecting the pads on one of said chips in said stack to said upper set of ends and the pads on the other of said chips in said stack to the lower set of ends with bonding wires to form a wire bonded chip stack, encapsulating said wire bonded chip stack with encapsulating so selected ones of leads have their outer ends extending out of said encapsulation, forming the outer ends of said leads extending out of said encapsulation.
Claim 3
Dependent Claim
28 words
The method as claimed in claim 1 further comprising the step of offsetting one of said chips relative to the other of said chips during said joining step.
Claim 4
Dependent Claim
25 words
The method as claimed in claim 1 wherein the pads of said chips are bonded to the respective ends of said leads by wire bonding.
Claim 5
Dependent Claim
70 words
A semiconductor module comprising: a housing, two chips having a plurality of pads thereon stacked together back-to-back in said housing to form a stack, leads electrically connected to the pads of said stacked chips by wire bonding, which leads have outer end substantially outside said housing and inner ends in said housing, which inner ends are formed into upper and lower sets having a gap therebetween for receiving said stack.
Claim 6
Dependent Claim
70 words
A semiconductor module comprising: a housing, two chips having a plurality of pads thereon stacked together back-to-back in said housing to form a stack, leads electrically connected to the pads of said stacked chips by wire bonding, which leads have outer end substantially outside said housing and inner ends in said housing, which inner ends are formed into upper and lower sets having a gap therebetween for receiving said stack.
Claim 7
Dependent Claim
149 words
A metallic lead frame for the mounting of and interconnection to a semiconductor chip comprising: a hollow rectangular selvedge, a plurality of inwardly directed lead frame fingers within the periphery of said selvedge, a selected number of said fingers being supported at both ends, and the remainder of said fingers having free unsupported ends, each said selected number of said fingers having first and second sections, the second section being at an angle to the first section of said finger and traversing the unsupported ends of a portion of the remainder of said fingers, said first and second sections being respectively connected to a respective adjacent sides of said rectangular selvedge, and the unsupported ends of the remainder of said fingers being split and the second section of said lead frame, traversing the unsupported ends of said remainder of said fingers, being provided with a plurality of short fingers.
Claim 8
Dependent Claim
149 words
A metallic lead frame for the mounting of and interconnection to a semiconductor chip comprising: a hollow rectangular selvedge, a plurality of inwardly directed lead frame fingers within the periphery of said selvedge, a selected number of said fingers being supported at both ends, and the remainder of said fingers having free unsupported ends, each said selected number of said fingers having first and second sections, the second section being at an angle to the first section of said finger and traversing the unsupported ends of a portion of the remainder of said fingers, said first and second sections being respectively connected to a respective adjacent sides of said rectangular selvedge, and the unsupported ends of the remainder of said fingers being split and the second section of said lead frame, traversing the unsupported ends of said remainder of said fingers, being provided with a plurality of short fingers.
Claim 9
Dependent Claim
32 words
The lead frame of claim 5 wherein the second section of said lead frame traversing the unsupported ends of said other lead frame fingers is connected to said selvedge at two points.
Claim 10
Dependent Claim
34 words
The lead frame of claim 5 wherein the second section of said lead frame finger that traverses the unsupported ends of the other lead frame fingers is connected to opposing sides of said selvedge.
References Cited (Backward Citations)
US4214120A
Cited
JPS56137665A
Cited
US4423468A
Cited
US4363076A
Cited
US4496965A
Cited
US4514750A
Cited
US4521828A
Cited
US4884237A
Cited
US4862245A
Cited
US4774635A
Cited
US4763188A
Cited
US4766478A
Cited
US4942455A
Cited
US4982265A
Cited
US4862322A
Cited
US4979016A
Cited
US5052481A
Cited
US4996583A
Cited
US4987473A
Cited
US4965654A
Cited
US5012323A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-12 | 1997-01-11 | 1997-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-12 | 2001-01-11 | 2001-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-12 | 2005-01-11 | 2005-07-13 | $7700.00 | Window Closed / Lapsed |