US5191402A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having an inter-layer insulating film disposed between two wiring layers
Assignee: Seiko Epson Corp
•
Filing: 1990-06-01
•
Granted: 1993-03-02
•
Expires: 2010-06-01
Abstract
Abstract A semiconductor device includes a substrate, first insulating film carried on the substrate, first wiring layer carried on the first insulating film and an interlayer insulating film overlying the first wiring layer and first insulating film. The interlayer insulating film has a top portion overlying the first wiring layer and a pair of sidewall portions. The sidewall portions of the interlayer insulating film overlie the first insulating film and the sides of the first wiring layer. The sidewall portions have progressively increasing width in progressing towards the substrate. The device also includes a second wiring layer which extends from overlying part of the top portion of the interlayer insulating film to and in contact with an exposed portion of the substrate adjacent to the first insulating film.
Inventors
- 👤 Toshihiko Kondo
- 👤 Kazuo Tanaka
- 👤 Hirofumi Yasuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:14
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H10B; H10B20/00; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10W20/071; H10W20/074; H10W20/075; H10W20/077; H10W20/40; H10W20/41; H10W20/425; H10W20/44; H10W20/4451
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
164 words
A semiconductor device comprising: a semiconductor substrate; a first insulating film carried on the semiconductor substrate; a first wiring layer having sides and carried on the first insulating film; an interlayer insulating film overlying the first wiring layer and the first insulating film, the interlayer insulating film having: a top portion which overlies the first wiring layer, and a pair of sidewall portions which overlie the first insulating film, are adjacent to and in contact with the sides of the first wiring layer, and, as viewed from an elevational perspective, increase in width in advancing from contact with the first wiring layer towards the substrate; and a second wiring layer which extends from overlying part of the top portion of the interlayer insulating film to and in contact with an exposed portion of the substrate adjacent the first insulating film; wherein a portion of the second wiring layer is in contact with a portion of at least one of the pair of sidewall portions.
Claim 2
Dependent Claim
164 words
A semiconductor device comprising: a semiconductor substrate; a first insulating film carried on the semiconductor substrate; a first wiring layer having sides and carried on the first insulating film; an interlayer insulating film overlying the first wiring layer and the first insulating film, the interlayer insulating film having: a top portion which overlies the first wiring layer, and a pair of sidewall portions which overlie the first insulating film, are adjacent to and in contact with the sides of the first wiring layer, and, as viewed from an elevational perspective, increase in width in advancing from contact with the first wiring layer towards the substrate; and a second wiring layer which extends from overlying part of the top portion of the interlayer insulating film to and in contact with an exposed portion of the substrate adjacent the first insulating film; wherein a portion of the second wiring layer is in contact with a portion of at least one of the pair of sidewall portions.
Claim 3
Dependent Claim
18 words
The semiconductor device according to claim 1, wherein the first wiring layer comprises a layer of polycrystalline silicon.
Claim 4
Dependent Claim
33 words
The semiconductor device according to claim 1, further including diffusion-layer regions in the surface of the semiconductor substrate contacted by the first insulating film and defining a source region and a drain region.
Claim 5
Dependent Claim
33 words
The semiconductor device according to claim 2, further including diffusion-layer regions in the surface of the semiconductor substrate contacted by the first insulating film and defining a source region and a drain region.
Claim 6
Dependent Claim
17 words
The semiconductor device according to claim 1, wherein said first wiring layer serves as a gate electrode.
Claim 7
Dependent Claim
18 words
The semiconductor device according to claim 1, wherein the second wiring layer comprises a layer of polycrystalline silicon.
Claim 8
Dependent Claim
18 words
The semiconductor device according to claim 2, wherein the second wiring layer comprises a layer of polycrystalline silicon.
Claim 9
Dependent Claim
18 words
The semiconductor device according to claim 3, wherein the second wiring layer comprises a layer of polycrystalline silicon.
Claim 10
Dependent Claim
18 words
The semiconductor device according to claim 4, wherein the second wiring layer comprises a layer of polycrystalline silicon.
Claim 11
Dependent Claim
18 words
The semiconductor device according to claim 5, wherein the second wiring layer comprises a layer of polycrystalline silicon.
Claim 12
Dependent Claim
17 words
The semiconductor device according to claim 2, wherein said first wiring layer serves as a gate electrode.
Claim 13
Dependent Claim
18 words
The semiconductor device according to claim 11, wherein the second wiring layer comprises a layer of polycrystalline silicon.
Claim 14
Dependent Claim
17 words
The semiconductor device according to claim 3, wherein said first wiring layer serves as a gate electrode.
Claim 15
Dependent Claim
18 words
The semiconductor device according to claim 13, wherein the second wiring layer comprises a layer of polycrystalline silicon.
Claim 16
Dependent Claim
17 words
The semiconductor device according to claim 4, wherein said first wiring layer serves as a gate electrode.
Claim 17
Dependent Claim
17 words
The semiconductor device according to claim 15, wherein the second wiring layer comprises a layer polycrystalline silicon.
References Cited (Backward Citations)
US4301518A
Cited
US4654680A
Cited
US4532534A
Cited
US4494301A
Cited
US4663645A
Cited
US4807002A
Cited
US4845544A
Cited
US4823172A
Cited
US4862233A
Cited
US4855801A
Cited
US4808544A
Cited
US4907046A
Cited
US5075762A
Cited
US4881107A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-01 | 1996-08-31 | 1997-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-01 | 2000-08-31 | 2001-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-01 | 2004-08-31 | 2005-03-02 | $7700.00 | Window Closed / Lapsed |