Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
155 words
A folded bit line configuration for a semiconductor memory device comprising a substrate having a plurality of spaced drain regions in the surface thereof, a conductive bit line stud disposed over and in contact with each of said plurality of drain regions, a pillar of conductive material disposed on each of said conductive bit line studs, each of said pillars having a first vertical side and a second vertical side opposite to said first vertical side, a layer of insulating material disposed on said first vertical side of every alternative ones of said plurality of pillars, a layer of insulating material disposed on said second vertical side of the other of said alternative ones of said plurality of pillars not having insulating material on said first side, conductive side wall spacer bit line rails disposed on both said first and second sides of said plurality of pillars and extending in parallel in a first direction.
Claim 2
Dependent Claim
155 words
A folded bit line configuration for a semiconductor memory device comprising a substrate having a plurality of spaced drain regions in the surface thereof, a conductive bit line stud disposed over and in contact with each of said plurality of drain regions, a pillar of conductive material disposed on each of said conductive bit line studs, each of said pillars having a first vertical side and a second vertical side opposite to said first vertical side, a layer of insulating material disposed on said first vertical side of every alternative ones of said plurality of pillars, a layer of insulating material disposed on said second vertical side of the other of said alternative ones of said plurality of pillars not having insulating material on said first side, conductive side wall spacer bit line rails disposed on both said first and second sides of said plurality of pillars and extending in parallel in a first direction.
Claim 3
Dependent Claim
87 words
A folded bit line configuration for a semiconductor memory device according to claim 1 further including a first plurality of sense amplifiers, each sense amplifier of said first plurality having an input connected to a separate pair of side wall spacer bit lines disposed on said first side of said pillars, and a second plurality of sense amplifiers, each sense amplifier of said second plurality having an input connected to a separate pair of side walls spacer bit lines disposed on said second side of said pillars.
Claim 4
Dependent Claim
90 words
A folded bit line configuration for a semiconductor memory device according to claim 2 wherein said first plurality of sense amplifiers are located in said semiconductor memory device at one end of said side wall spacer bit line pairs and said second plurality of sense amplifiers are located in said semiconductor memory device at the other end of said side wall spacer bit line pairs such that said bit line pairs extend between said first plurality of sense amplifiers and said second plurality of sense amplifiers in said memory device.
Claim 5
Dependent Claim
76 words
A folded bit line configuration for a semiconductor memory device according to claim 3 further including a plurality of word line pairs each including first and second word lines disposed on said substrate on either side of said bit line studs in parallel in a direction orthogonal to said first direction of said bit lines, said bit line pairs and said word line pairs form a multi-layer configuration of bit line and word line crossover positions.
Claim 6
Dependent Claim
44 words
A folded bit line configuration for a semiconductor memory device according to claim 4 further including a memory cell located at each of said crossover positions, and wherein adjacent ones of said memory cells share a common drain junction and bit line contact stud.