Bit line structure of dynamic type semiconductor memory device

Claim 2

An improvement of a bit line structure in a semiconductor memory device having a folded bit line structure, comprising: a substrate; a plurality of bit line pairs each divided into a plurality of blocks of bit line pairs along a longitudinal direction of said substrate; wherein each divided bit line pair within a common block is formed by an interconnection layer at a level above said substrate which is different from the level of an adjacent divided bit line pair in the same block and different from the level of the same bit line pair in an adjacent block.

Claim 3

The improvement of claim 1, wherein sense amplifiers of successive bit line pairs are located in different blocks.

Claim 4

The improvement of claim 1, wherein portions of each of said divided bit line pairs in successive blocks are located alternately at first and second different levels above said substrate, and further wherein successive bit line pairs in a common block are located alternately at said first and second different levels above said substrate.

Claim 5

The improvement of claim 1, wherein each of said bit line pairs is formed of the same conductive material.

Claim 6

The improvement of claim 1, wherein each divided bit line pair in one block is made of a conducting material different from the conducting material of an adjacent divided bit line pair in the same block.

Claim 7

The improvement of claim 1, wherein sense amplifiers are connected respectively to adjacent bit line pairs in a common block at different levels above said substrate.

Claim 8

The improvement of claim 1, wherein portions of each of said divided bit line pairs at said first and second levels above said substrate are made respectively of different conducting materials, and wherein sense amplifiers are connected respectively to common conductiing materials of said bit line pairs.

Claim 9

The improvement of claim 7, wherein sense amplifiers of successive bit line pairs are located alternately in successive blocks.

Claim 10

The improvement of claim 7, wherein one of said conducting materials is aluminum, and said sense amplifiers are connected to portions of said divided bit line pairs formed of aluminum.

Claim 11

The improvement of claim 9, wherein other portions of each of said divided bit line pairs are formed of polysilicon.

Claim 12

The improvement of claim 9, wherein portions of each of said divided bit line pairs in a common block are formed of the same conducting material.

Claim 13

A folded-bit line type semiconductor memory device, comprising: a substrate; a plurality of word lines formed on an insulator disposed on said substrate; a plurality of bit line pairs crossing said plurality of word lines, memory cells provided at crossings of said pluralities of word lines and bit line pairs; row decoder means responsive to an external address signal for selecting one word line out of said plurality of word lines; column decoder means responsive to said external address signal for selecting one bit one pair out of said plurality of bit line pairs; said plurality of bit line pairs being divided longitudinally into a plurality of blocks of bit line pairs; a plurality of sense amplifiers connected respectively to said plurality of bit line pairs for amplifying a potential difference between the bit lines of corresponding bit line pairs; the bit lines of a first one of said bit line pairs in one of said plurality of blocks being located at a common first level above said substrate; the bit lines of a second one of said bit line pairs in said one block of said plurality of blocks adjacent said first one of said bit line pairs and the bit lines of said first one of said bit line pairs in an adjacent block being located at a common second level different from said first level above said substrate.

Claim 14

A folded-bit line type semiconductor memory device, comprising: a substrate; a plurality of word lines formed on an insulator disposed on said substrate; a plurality of bit line pairs crossing said plurality of word lines, memory cells provided at crossings of said pluralities of word lines and bit line pairs; row decoder means responsive to an external address signal for selecting one word line out of said plurality of word lines; column decoder means responsive to said external address signal for selecting one bit one pair out of said plurality of bit line pairs; said plurality of bit line pairs being divided longitudinally into a plurality of blocks of bit line pairs; a plurality of sense amplifiers connected respectively to said plurality of bit line pairs for amplifying a potential difference between the bit lines of corresponding bit line pairs; the bit lines of a first one of said bit line pairs in one of said plurality of blocks being located at a common first level above said substrate; the bit lines of a second one of said bit line pairs in said one block of said plurality of blocks adjacent said first one of said bit line pairs and the bit lines of said first one of said bit line pairs in an adjacent block being located at a common second level different from said first level above said substrate.

Claim 15

An improvement of a bit line structure in a semiconductor memory device having a folded bit line structure, comprising: a substrate; a plurality of bit line pairs comprising odd bit line pairs and even line pairs above said substrate; the bit lines of said odd bit lines having a first portion thereof located at a common first level above said substrate and an adjacent second portion thereof located at a common second level above said substrate different from said first level; the bit lines of said even bit line pairs having a first portion thereof adjacent, and located at a different level above said substrate from, the first portion of the bit lines of at least one of said odd bit line pairs and a second portion thereof adjacent, and located at a different level above said substrate from, the second portion of the bit lines of said at least one of said odd bit line pairs; said first and second portions of the bit lines of said odd bit line pairs being located at different levels above said substrate; and said first and second portions of the bit lines of said even bit line pairs being located at different levels above said substrate.

Claim 16

An improvement of a bit line structure in a semiconductor memory device having a folded bit line structure, comprising: a substrate; a plurality of bit line pairs comprising odd bit line pairs and even line pairs above said substrate; the bit lines of said odd bit lines having a first portion thereof located at a common first level above said substrate and an adjacent second portion thereof located at a common second level above said substrate different from said first level; the bit lines of said even bit line pairs having a first portion thereof adjacent, and located at a different level above said substrate from, the first portion of the bit lines of at least one of said odd bit line pairs and a second portion thereof adjacent, and located at a different level above said substrate from, the second portion of the bit lines of said at least one of said odd bit line pairs; said first and second portions of the bit lines of said odd bit line pairs being located at different levels above said substrate; and said first and second portions of the bit lines of said even bit line pairs being located at different levels above said substrate.

Claim 17

The improvement of claim 13, including first sense amplifiers respectively connected to said first portions of said odd bit line pairs and second sense amplifiers respectively connected to said second portions of said even bit line pairs.

Claim 18

The improvement of claim 14, including first sense amplifiers respectively connected to said first portions of said even bit line pairs and second sense amplifiers respectively connected to said second portions of said odd bit line pairs.