Semiconductor memory

Claim 2

A semiconductor folded bit line memory for a plurality of bits comprising: a plurality of word lines comprised of a metal and arranged in parallel with each other in a predetermined direction, at least first through fourth sequentially arranged bit lines arranged in parallel with each other and forming a plurality of folded bit line pairs in a direction generally orthogonal to said predetermined direction, a plurality of memory cells, each of which is arranged in correspondence with one of a plurality of cross points between each of said word lines and said bit lines, each of said bits being structured as an interconnected pair of first and second ones of said memory cells having signal path connections to said first and third bit lines or to said second and fourth bit lines for redundant storage of data in a complementary manner; first and second sense amplifying means connected to said first and third bit lines and to said second and fourth bit lines, respectively, thereby forming said first and third bit lines into one pair of folded bit lines and forming said second and fourth bit lines into another pair of folded bit lines, said sense amplifying means operable for amplifying a signal applied to said respective bit lines from selected first and second memory cells.

Claim 3

A semiconductor memory in accordance with claim 1 wherein said first sense amplifying means is disposed at one end of each bit line and said second sense amplifying means is disposed at the other end of each bit line.

Claim 4

A semiconductor memory in accordance with claim 1 including dummy bit structures each having a pair of dummy memory cells connected via different bit lines to different sense amplifying means.

Claim 5

A multi-bit folded bit line memory structure comprising: a plurality of two-cell bit structures; a plurality of sense amplifiers, alternate amplifiers located at opposite ends of a plurality of bit lines; each sense amplifier sensing signals on a corresponding pair of alternate bit lines; said bit structures arranged in a plurality of sets; differing cells of each of said bit structures of any single set having signal path connections to a particular pair of corresponding bit lines connected to different ones of a single pair of sense amplifiers.

Claim 6

A multi-bit folded bit line memory structure comprising: a plurality of two-cell bit structures; a plurality of sense amplifiers, alternate amplifiers located at opposite ends of a plurality of bit lines; each sense amplifier sensing signals on a corresponding pair of alternate bit lines; said bit structures arranged in a plurality of sets; differing cells of each of said bit structures of any single set having signal path connections to a particular pair of corresponding bit lines connected to different ones of a single pair of sense amplifiers.

Claim 7

A multi-bit folded bit line memory structure comprising: a plurality of folded bit line pairs; a plurality of two-cell bit structures; a plurality of sense amplifiers having corresponding terminals connected to opposite ends of alternate ones of a plurality of corresponding sequential bit lines thereby forming said folded bit line pairs as pairs of alternate ones of said corresponding bit lines; said bit structures arranged in two sets, differing cells of a first set of bit structures having signal path connections to consecutive coresponding bit lines connected to different sense amplifiers, respectively; and differing cells of a second set of bit structures having signal path connections to consecutive opposite bit lines connected to different sense amplifiers, respectively; at least one bit line connected to cells of bit structure of different sets.

Claim 8

A multi-bit folded bit line memory structure comprising: a plurality of folded bit line pairs; a plurality of two-cell bit structures; a plurality of sense amplifiers having corresponding terminals connected to opposite ends of alternate ones of a plurality of corresponding sequential bit lines thereby forming said folded bit line pairs as pairs of alternate ones of said corresponding bit lines; said bit structures arranged in two sets, differing cells of a first set of bit structures having signal path connections to consecutive coresponding bit lines connected to different sense amplifiers, respectively; and differing cells of a second set of bit structures having signal path connections to consecutive opposite bit lines connected to different sense amplifiers, respectively; at least one bit line connected to cells of bit structure of different sets.

Claim 9

A twin cell multi-bit folded bit line memory structure including: a plurality of folded bit line pairs; at least 4 interleaved bit lines; two memory cells per bit; a pair of sense amplifying means associated with said bit lines; each of said sense amplifying means exclusively connected to a pair of alternate bit lines thereby forming said folded bit line pairs as pairs of alternate ones of said bit lines; said two memory cells of each bit having signal path connections to consecutive ones of said bit lines connected to different sense amplifying means.

Claim 10

A twin cell multi-bit folded bit line memory structure including: a plurality of folded bit line pairs; at least 4 interleaved bit lines; two memory cells per bit; a pair of sense amplifying means associated with said bit lines; each of said sense amplifying means exclusively connected to a pair of alternate bit lines thereby forming said folded bit line pairs as pairs of alternate ones of said bit lines; said two memory cells of each bit having signal path connections to consecutive ones of said bit lines connected to different sense amplifying means.

Claim 11

A memory structure in accordance with claim 6 including dummy bit structures each having a pair of dummy memory cells connected via different bit lines to different sense amplifying means.

Claim 12

A semiconductor folded bit line memory for a plurality of bits comprising: a plurality of word lines comprised of a metal and arranged in parallel with each other in a predetermined direction, a plurality of folded bit line pairs formed of at least first through fourth bit lines sequentially arranged in parallel with each other in a direction generally orthogonal to said predetermined direction, a plurality of memory cells, each of which is arranged in correspondence with one of a plurality of cross points between each of said word lines and said bit lines, each of said bits being structured as an interconnected pair of first and second ones of said memory cells having signal path connections to said first and third bit lines or to said second and fourth bit lines; said word lines further comprising transfer gate means connected to pairs of said memory cells, first and second sense amplifying means having signal path connections to said first and third bit lines and to said second and fourth bit lines, respectively, thereby forming said first and third bit lines into one pair of folded bit lines and forming said second and fourth bit lines into another pair of folded bit lines, said sense amplifying means operable for amplifying a signal applied to said respective bit lines from selected first and second memory cells connected directly thereto, said first and second sense amplifying means disposed at opposite ends of said bit lines.

Claim 13

A semiconductor folded bit line memory for a plurality of bits comprising: a plurality of word lines comprised of a metal and arranged in parallel with each other in a predetermined direction, a plurality of folded bit line pairs formed of at least first through fourth bit lines sequentially arranged in parallel with each other in a direction generally orthogonal to said predetermined direction, a plurality of memory cells, each of which is arranged in correspondence with one of a plurality of cross points between each of said word lines and said bit lines, each of said bits being structured as an interconnected pair of first and second ones of said memory cells having signal path connections to said first and third bit lines or to said second and fourth bit lines; said word lines further comprising transfer gate means connected to pairs of said memory cells, first and second sense amplifying means having signal path connections to said first and third bit lines and to said second and fourth bit lines, respectively, thereby forming said first and third bit lines into one pair of folded bit lines and forming said second and fourth bit lines into another pair of folded bit lines, said sense amplifying means operable for amplifying a signal applied to said respective bit lines from selected first and second memory cells connected directly thereto, said first and second sense amplifying means disposed at opposite ends of said bit lines.

Claim 14

A semiconductor folded bit line memory structure as recited in claim 8 further comprising transfer gate means formed in a polysilicon layer and contact means for providing contact between said metal word lines and said transfer gate means.

Claim 15

A semiconductor folded bit line memory structure as recited in claim 6, further comprising a plurality of word lines comprised of a metal and arranged substantially perpendicularly to said bit lines, transfer gate means formed in a polysilicon layer and contact means for providing contact between said metal word lines and said transfer gate means.

Claim 16

A semiconductor folded bit line memory structure as recited in claim 5, further comprising a plurality of word lines comprised of a metal and arranged substantially perpendicularly to said bit lines, transfer gate means formed in a polysilicon layer and contact means for providing contact between said metal word lines and said transfer gate means.

Claim 17

A semiconductor folded bit line memory structure as recited in claim 4, further comprising a plurality of word lines comprised of a metal and arranged substantially perpendicularly to said bit lines, transfer gate means formed in a polysilicon layer and contact means for providing contact between said metal word lines and said transfer gate means.

Claim 18

A semiconductor folded bit line memory structure as recited in claim 1 further comprising transfer gate means formed in a polysilicon layer and contact means for providing contact between said metal word lines and said transfer gate means.