Semiconductor memory device with wirings having ensured cross-sections

Claim 1

A semiconductor memory device comprising: a semiconductor substrate; a plurality of memory cell structures formed on said semiconductor substrate, each memory cell having a transistor which has a drain region; a plurality of wiring groups formed above said memory cell structures, said wiring groups forming data line wirings, which extend parallel along a first predetermined direction, an forming word line wirings, which extend in parallel along a second predetermined direction; and insulating layers provided between said wirings of said wiring groups, said data line wirings being distributed between an upper layer and a lower layer, said upper layer and said lower layer being separated by one of said insulating layers, said upper and lower layers being formed from the same material, said data line wirings distributed in said upper layer being arranged in an overlapping relationship with regard to said data line wirings distributed in said lower layer, wherein said data line wirings contact said drain regions of said transistors of associated memory cells, respectively.