High density read only memory

Claim 2

A ROM matrix comprising: a semiconductor substrate, a plurality of columns of seriesed FETs disposed in parallel in the substrate, certain FETs having implanted channels causing them to operate in the depletion mode, the remaining FETs being operable in the enhancement mode, and a plurality of conductive layers disposed in rows transverse to the columns for accessing each FET to determine its mode, the conductive layers being closely packed so that adjacent FETs have abutting channels.

Claim 3

The ROM matrix of claim 1 wherein the conductive layers comprise heavily doped polysilicon.

Claim 4

A ROM matrix comprising: a silicon substrate of a first conductivity type, a plurality of parallel columns of active areas disposed in the substrate, a first oxide layer disposed on the substrate above the columns, a first group of doped polysilicon layers disposed on the first oxide layer in regularly spaced rows transverse to the columns, a second oxide layer disposed over the first polysilicon layers, a second group of rows of doped polysilicon layers insulated from the substrate and from the first polysilicon layers by the oxide layers, the second polysilicon layers being disposed in the spaces in between the rows of the first polysilicon layers, a plurality of depletion mode field-effect transistors formed at selected intersections of the rows and columns, and a plurality of enhancement mode field-effect transistors formed at the nonselected intersections.

Claim 5

A ROM matrix comprising: a silicon substrate of a first conductivity type, a plurality of parallel columns of active areas disposed in the substrate, a first oxide layer disposed on the substrate above the columns, a first group of doped polysilicon layers disposed on the first oxide layer in regularly spaced rows transverse to the columns, a second oxide layer disposed over the first polysilicon layers, a second group of rows of doped polysilicon layers insulated from the substrate and from the first polysilicon layers by the oxide layers, the second polysilicon layers being disposed in the spaces in between the rows of the first polysilicon layers, a plurality of depletion mode field-effect transistors formed at selected intersections of the rows and columns, and a plurality of enhancement mode field-effect transistors formed at the nonselected intersections.

Claim 6

The ROM matrix of claim 3 wherein the second polysilicon layers partially overlap the first polysilicon layers.

Claim 7

The ROM matrix of claim 3 wherein the depletion mode transistors have channels of implanted impurities of a second conductivity type.

Claim 8

The ROM matrix of claim 3 wherein adjacent transistors in the columns have abutting channels.

Claim 11

The method of claim 7 wherein in step (c) the transistor channels of the second conductivity type are formed by ion implantation.

Claim 12

The method of claim 7 wherein the conductive layers are formed by depositing polysilicon and selectively etching the polysilicon into rows, and the second group of layers are insulated from the first group by an oxide layer grown on the layers of the first group.