Semiconductor memory device

Claim 2

A semiconductor memory device characterized by comprising a semiconductor substrate (11) of a first conductivity type; a plurality of first polycrystalline silicon layers (15) insulatively disposed over said semiconductor substrate (11) and forming capacitors in cooperation with said substrate; second polycrystalline silicon layers (16) formed on said semiconductor substrate and functioning as digit lines; regions (17) of a second conductivity type formed at parts of said semiconductor substrate immediately below said second polycrystalline silicon layers (16); and third polycrystalline silicon layers (20) insulatively disposed over said semiconductor substrate between said first and second polycrystalline silicon layers (15, 16) and functioning as gates of MOS transistors.

Claim 3

A semiconductor memory device as claimed in claim 1, characterized in that an impurity of the second conductivity type is doped in said second polycrystalline silicon layers (16), and said regions (17) of the second conductivity type are formed by diffusion of said impurity of the second conductivity type in said second polycrystalline silicon layers.

Claim 4

A semiconductor memory device characterized by comprising a semiconductor substrate (11) of the first conductivity type; a first insulative layer (14) formed on said semiconductor substrate (11) and having a plurality of openings; a plurality of first polycrystalline silicon layers (15) selectively formed on said first insulative layer (14) and forming a plurality of capacitors in cooperation with said semiconductor substrate (11); second polycrystalline silicon layers (16) formed to be in contact with said semiconductor substrate (11) through said openings in said first insulative layer, said second polycrystalline silicon layers being insulated from said first polycrystalline silicon layers (15) and functioning as digit lines; regions (17) of the second conductivity type formed at parts of said semiconductor substrate (11) which are in contact with said second polycrystalline silicon layers (16); and a plurality of third polycrystalline silicon layers (20) insulatively disposed over said semiconductor substrate between said second polycrystalline silicon layers which are in contact with said semiconductor substrate and said first polycrystalline silicon layers, said plurality of third polycrystalline silicon layers functioning as gates of said MOS transistors.

Claim 5

A semiconductor memory device characterized by comprising a semiconductor substrate (11) of the first conductivity type; a first insulative layer (14) formed on said semiconductor substrate (11) and having a plurality of openings; a plurality of first polycrystalline silicon layers (15) selectively formed on said first insulative layer (14) and forming a plurality of capacitors in cooperation with said semiconductor substrate (11); second polycrystalline silicon layers (16) formed to be in contact with said semiconductor substrate (11) through said openings in said first insulative layer, said second polycrystalline silicon layers being insulated from said first polycrystalline silicon layers (15) and functioning as digit lines; regions (17) of the second conductivity type formed at parts of said semiconductor substrate (11) which are in contact with said second polycrystalline silicon layers (16); and a plurality of third polycrystalline silicon layers (20) insulatively disposed over said semiconductor substrate between said second polycrystalline silicon layers which are in contact with said semiconductor substrate and said first polycrystalline silicon layers, said plurality of third polycrystalline silicon layers functioning as gates of said MOS transistors.

Claim 6

A semiconductor memory device as claimed in claim 3, characterized in that said first insulative layer (14) comprises thin insulative layers (14a) and thick insulative layers (14b), and said capacitors are formed between said first polycrystalline silicon layers on said thin insulative layers and said semiconductor substrate.

Claim 7

A semiconductor memory device as claimed in claim 4, characterized in that said thin insulative layers (14a) are Si0 2 layers of 500 to 1,000 A thickness, and said thick insulative layers (14b) are Si0 2 layers of 5,000 to 10,000 A thickness.

Claim 8

A semiconductor memory device as claimed in claim 3, characterized in that said second polycrystalline silicon layers (16) are so formed that they are alternately disposed on a second insulative layer (18) formed on said first polycrystalline silicon layers (15) and on said semiconductor substrate through said openings of said first insulative layer.

Claim 9

A semiconductor memory device as claimed in claim 3, 4, 5 or 6, characterized in that an impurity of the second conductivity type is doped in said second polycrystalline silicon layers (16), and said regions (17) of the second conductivity type are formed by diffusing said impurity of the second conductivity type from said second polycrystalline silicon layers.

Claim 10

A semiconductor memory device as claimed in claim 3, 4, 5 or 6, characterized in that recesses are selectively formed in said semiconductor substrate (11), field inversion preventive layers (12) are formed in said respective recesses, and said second polycrystalline silicon layers have recesses corresponding to said recesses.

Claim 11

A semiconductor memory device characterized by comprising a semiconductor substrate (11) of a first conductivity type; field inversion preventive regions (12) selectively formed in said semiconductor substrate (11); field inversion regions (13) formed at both sides of said field inversion preventive regions; a first insulative layer (14) formed on said semiconductor substrate and having a plurality of openings; a plurality of first polycrystalline silicon layers (15) formed on said field inversion preventive layers and said field inversion layers through said first insulative layer, said plurality of first polycrystalline silicon layers forming capacitors in cooperation with said field inversion layers; second insulative layers (18), respectively, formed on said first polycrystalline silicon layers; second polycrystalline silicon layers (16) alternately disposed on said second insulative layers (18) and on parts of said semiconductor substrate which are exposed through said openings in said first insulative layer (14), said second polycrystalline silicon layers functioning as digit lines; regions of the second conductivity type formed at parts of said semiconductor substrate which are in contact with said second polycrystalline silicon layers; and third polycrystalline silicon layers (20) insulatively disposed over said semiconductor substrate between said first polycrystalline silicon layers and said second polycrystalline silicon layers, said third polycrystalline silicon layers functioning as gates of MOS transistors.

Claim 12

A semiconductor memory device characterized by comprising a semiconductor substrate (11) of a first conductivity type; field inversion preventive regions (12) selectively formed in said semiconductor substrate (11); field inversion regions (13) formed at both sides of said field inversion preventive regions; a first insulative layer (14) formed on said semiconductor substrate and having a plurality of openings; a plurality of first polycrystalline silicon layers (15) formed on said field inversion preventive layers and said field inversion layers through said first insulative layer, said plurality of first polycrystalline silicon layers forming capacitors in cooperation with said field inversion layers; second insulative layers (18), respectively, formed on said first polycrystalline silicon layers; second polycrystalline silicon layers (16) alternately disposed on said second insulative layers (18) and on parts of said semiconductor substrate which are exposed through said openings in said first insulative layer (14), said second polycrystalline silicon layers functioning as digit lines; regions of the second conductivity type formed at parts of said semiconductor substrate which are in contact with said second polycrystalline silicon layers; and third polycrystalline silicon layers (20) insulatively disposed over said semiconductor substrate between said first polycrystalline silicon layers and said second polycrystalline silicon layers, said third polycrystalline silicon layers functioning as gates of MOS transistors.

Claim 13

A semiconductor memory device as claimed in claim 9, characterized in that said first insulative layer comprises thick insulative layer parts (14b) corresponding to said field inversion preventive regions and thin insulative layer parts (14a) corresponding to said field inverted regions.

Claim 14

A semiconductor memory device as claimed in claim 9 or 10, characterized in that said semiconductor substrate (11) has a plurality of selectively formed recesses and said field inversion preventive regions (12) are formed in said recesses.

Claim 15

A semiconductor memory device as claimed in claim 10, characterized in that said thick insulative (14b) layer parts of said first insulative layer (14) are formed by Si0 2 layers of 5,000 to 10,000 A thickness and said thin insulative layer parts (14a) are formed by Si0 2 layers of 500 to 1,000 A thickness.

Claim 16

A semiconductor memory device as claimed in claim 9, 10 or 12, characterized in that said regions of the first conductivity type are formed at the parts of said semiconductor substrate between said field inversior layers and said regions of the second conductivity type.

Claim 17

A semiconductor memory device as claimed in claim 13, characterized in that said regions of the first conductivity type have an impurity concentration of 1 to 5 x 1 0 10 cm -2 .

Claim 18

A semiconductor memory device as claimed in claim 9, 10, 12 or 14, characterized in that third polycrystalline silicon layers are so formed as to partially overlap said first and second polycrystalline silicon layers.

Claim 19

A semiconductor memory device as claimed in claim 9, 10, 12 or 14, characterized in that a passivation layer is formed on the entire device.

Claim 20

A semiconductor memory device as claimed in claim 9, 10, 12 or 14, characterized in that an impurity of the second conductivity type is doped in said second polycrystalline silicon layers, and said regions of the second conductivity type are formed by diffusing said impurity of the second conductivity type from said second polycrystalline silicon layers.