Electrically programmable nonvolatile semiconductor memory device with nand cell structure

Claim 2

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having row lines and column lines, each memory cell including cell transistors connected in series, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, and the control gates of the cell transistors in the same row being commonly connected to one of the row lines; row selection means for selecting one of the row lines in response to a row selection signal; column selection means for selecting one of the column lines in response to a column selection signal; and data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate by utilizing a tunnel effect, and emitting electrons through the insulation film from the floating gate by utilizing a tunnel effect.

Claim 3

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having row lines and column lines, each memory cell including cell transistors connected in series, and each of the cell transistors having a control gate, a floating gate, a channel region and a tunnel insulation film including a portion having a thickness sufficient to allow an electron tunnel effect to occur between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, and the control gates of the cell transistors in the same row being commonly connected to one of the row lines; row selection means for selecting one of the row lines in response to a row selection signal; column selection means for selecting one of the column lines in response to a column selection signal; and data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the tunnel insulation film from the floating gate.

Claim 4

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having row lines and column lines, each memory cell including cell transistors connected in series, and each of the cell transistors having a control gate, a floating gate, a channel region and a tunnel insulation film including a portion having a thickness sufficient to allow an electron tunnel effect to occur between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, and the control gates of the cell transistors in the same row being commonly connected to one of the row lines; row selection means for selecting one of the row lines in response to a row selection signal; column selection means for selecting one of the column lines in response to a column selection signal; and data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the tunnel insulation film from the floating gate.

Claim 5

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having row lines and column lines, each memory cell including cell transistors connected in series, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film on the entire channel region, the insulation film being thin enough to allow an electron tunnel effect to occur between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, and the control gates of the cell transistors in the same row being commonly connected to one of the row lines; row selection means for selecting one of the row lines in response to a row selection signal; column selection means for selecting one of the column lines in response to a column selection signal; and data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate.

Claim 6

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having row lines and column lines, each memory cell including cell transistors connected in series, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film on the entire channel region, the insulation film being thin enough to allow an electron tunnel effect to occur between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, and the control gates of the cell transistors in the same row being commonly connected to one of the row lines; row selection means for selecting one of the row lines in response to a row selection signal; column selection means for selecting one of the column lines in response to a column selection signal; and data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate.

Claim 7

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having row lines and column lines, each memory cell including cell transistors connected in series, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, and the control gates of the cell transistors in the same row being commonly connected to one of the row lines; row selection means for selecting one of the row lines in response to a row selection signal; column selection means for selecting one of the column lines in response to a column selection signal; and data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of setting the control gate at a potential higher than that of the channel region to inject electrons into the floating gate, and setting the control gate at a potential lower than that of the channel region to emit electrons from the floating gate.

Claim 8

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having row lines and column lines, each memory cell including cell transistors connected in series, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, and the control gates of the cell transistors in the same row being commonly connected to one of the row lines; row selection means for selecting one of the row lines in response to a row selection signal; column selection means for selecting one of the column lines in response to a column selection signal; and data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of setting the control gate at a potential higher than that of the channel region to inject electrons into the floating gate, and setting the control gate at a potential lower than that of the channel region to emit electrons from the floating gate.

Claim 9

A nonvolatile semiconductor memory device according to claim 3, wherein the insulation film is formed uniformly on the channel region.

Claim 10

A nonvolatile semiconductor memory device according to any one of claims 1 to 5, further comprising selection transistors respectively inserted between the first terminals of the memory cells and the column lines, for selecting one of the memory cells, the gates of the selection transistors being connected to one of the row lines.

Claim 11

A nonvolatile semiconductor memory device according to any one of claims 1 to 5, further comprising switching means respectively inserted between the second terminals of the memory cells and the reference potential, and controlled so as to be in an off state when the data programming means stores data.

Claim 12

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell being constituted between a first terminal and a second terminal by cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, wherein the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor is connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate by utilizing a tunnel effect, and emitting electrons through the insulation film from the floating gate by utilizing a tunnel effect; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to the second row line; column selection means for selecting one of the column lines in response to a column selection signal; and switching means connected between each of the second terminals of the memory cells and a reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data.

Claim 13

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell being constituted between a first terminal and a second terminal by cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, wherein the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor is connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate by utilizing a tunnel effect, and emitting electrons through the insulation film from the floating gate by utilizing a tunnel effect; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to the second row line; column selection means for selecting one of the column lines in response to a column selection signal; and switching means connected between each of the second terminals of the memory cells and a reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data.

Claim 14

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell being constituted between a first terminal and a second terminal by cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and a tunnel insulation film including a portion having a thickness sufficient to allow an electron tunnel effect to occur between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, wherein the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the control gates of the cell transistors in the same row are commonly connected to one of the first row lines, and the gate of the selection transistor is connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the tunnel insulation film into the floating gate, and emitting electrons through the tunnel insulation film from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to the second row line; column selection means for selecting one of the column lines in response to a column selection signal; and switching means connected between each of the second terminals of the memory cells and a reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data.

Claim 15

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell being constituted between a first terminal and a second terminal by cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and a tunnel insulation film including a portion having a thickness sufficient to allow an electron tunnel effect to occur between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, wherein the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the control gates of the cell transistors in the same row are commonly connected to one of the first row lines, and the gate of the selection transistor is connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the tunnel insulation film into the floating gate, and emitting electrons through the tunnel insulation film from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to the second row line; column selection means for selecting one of the column lines in response to a column selection signal; and switching means connected between each of the second terminals of the memory cells and a reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data.

Claim 16

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell being constituted between a first terminal and a second terminal by cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film on the entire channel region, for electrically storing data by using charges stored in the floating gate, wherein the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the control gates of the cell transistors in the same row are commonly connected to one of the first row lines, and the gate of the selection transistor is connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to the second row line; column selection means for selecting one of the column lines in response to a column selection signal; and switching means connected between each of the second terminals of the memory cells and a reference potential, for disconnecting the memory cell from a reference potential when the data programming means stores data.

Claim 17

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell being constituted between a first terminal and a second terminal by cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film on the entire channel region, for electrically storing data by using charges stored in the floating gate, wherein the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the control gates of the cell transistors in the same row are commonly connected to one of the first row lines, and the gate of the selection transistor is connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to the second row line; column selection means for selecting one of the column lines in response to a column selection signal; and switching means connected between each of the second terminals of the memory cells and a reference potential, for disconnecting the memory cell from a reference potential when the data programming means stores data.

Claim 18

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell being constituted between a first terminal and a second terminal by cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, wherein the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the control gates of the cell transistors in the same row are commonly connected to one of the first row lines, and the gate of the selection transistor is connected to one of the second row lines; data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of setting the control gate a potential higher then that of the channel region to inject electrons into the floating gate, and setting the control gate at a potential lower than that of the channel region to emit electrons from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting one of the cell transistors connected to the second row lines; column selection means for selecting one of the column lines in response to a column selection signal; and switching means connected between each of the second terminals of the memory cells and a reference potential, for disconnecting the memory cell from a reference potential when the data programming means stores data.

Claim 19

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell being constituted between a first terminal and a second terminal by cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, wherein the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the control gates of the cell transistors in the same row are commonly connected to one of the first row lines, and the gate of the selection transistor is connected to one of the second row lines; data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of setting the control gate a potential higher then that of the channel region to inject electrons into the floating gate, and setting the control gate at a potential lower than that of the channel region to emit electrons from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting one of the cell transistors connected to the second row lines; column selection means for selecting one of the column lines in response to a column selection signal; and switching means connected between each of the second terminals of the memory cells and a reference potential, for disconnecting the memory cell from a reference potential when the data programming means stores data.

Claim 20

A nonvolatile semiconductor memory device according to claim 11, wherein the insulation film is formed uniformly on the channel region.

Claim 21

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column line, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate by utilizing a tunnel effect, and emitting electrons through the insulation film from the floating gate by utilizing a tunnel effect; row selection means for selecting at least one of the second row lines to select at least one of the selection transistors, and to apply a cell selection signal to at least one of the cell transistors; and column selection means for selecting one of the column lines in response to a column address signal from an external source.

Claim 22

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column line, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate by utilizing a tunnel effect, and emitting electrons through the insulation film from the floating gate by utilizing a tunnel effect; row selection means for selecting at least one of the second row lines to select at least one of the selection transistors, and to apply a cell selection signal to at least one of the cell transistors; and column selection means for selecting one of the column lines in response to a column address signal from an external source.

Claim 23

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistors for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and a tunnel insulation film including a portion having a thickness sufficient to cause a tunnel effect between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the tunnel insulation film into the floating gate, and emitting electrons through the tunnel insulation film from the floating gate; row selection means for selecting at least one of the second row lines to select at least one of the selection transistors, and to apply a cell selection signal to at least one of the cell transistors; and column selection means for selecting one of the column lines in response to a column address signal from an external source.

Claim 24

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistors for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and a tunnel insulation film including a portion having a thickness sufficient to cause a tunnel effect between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the tunnel insulation film into the floating gate, and emitting electrons through the tunnel insulation film from the floating gate; row selection means for selecting at least one of the second row lines to select at least one of the selection transistors, and to apply a cell selection signal to at least one of the cell transistors; and column selection means for selecting one of the column lines in response to a column address signal from an external source.

Claim 25

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistors for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film on the entire channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, each of the selection transistors being connected between one end of the cell transistors connected in series and one of the column lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate; row selection means for selecting at least one of the second row lines to select at least one of the selection transistors, and to apply a cell selection signal to at least one of the cell transistors; and column selection means for selecting one of the column lines in response to a column address signal from an external source.

Claim 26

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistors for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film on the entire channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, each of the selection transistors being connected between one end of the cell transistors connected in series and one of the column lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate; row selection means for selecting at least one of the second row lines to select at least one of the selection transistors, and to apply a cell selection signal to at least one of the cell transistors; and column selection means for selecting one of the column lines in response to a column address signal from an external source.

Claim 27

A nonvolatile semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell in the memory cell array including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cells having a control gate, a floating gate, a channel region and an insulation film formed between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, each of the selection transistors being connected between one end of the cell transistors connected in series and one of the column lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of setting the control gate at a potential higher than that of the channel region to inject electrons into the floating gate, and setting the control gate at a potential lower than that of the channel region to emit electrons from the floating gate; row selection means for selecting at least one of the second row lines to select at least one of the selection transistors, and to apply a cell selection signal to at least one of the cell transistors; and column selection means for selecting one of the column lines in response to a column address signal from an external source.

Claim 28

A nonvolatile semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell in the memory cell array including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cells having a control gate, a floating gate, a channel region and an insulation film formed between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, each of the selection transistors being connected between one end of the cell transistors connected in series and one of the column lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of setting the control gate at a potential higher than that of the channel region to inject electrons into the floating gate, and setting the control gate at a potential lower than that of the channel region to emit electrons from the floating gate; row selection means for selecting at least one of the second row lines to select at least one of the selection transistors, and to apply a cell selection signal to at least one of the cell transistors; and column selection means for selecting one of the column lines in response to a column address signal from an external source.

Claim 29

A nonvolatile semiconductor memory device according to any one of claims 13 to 16, wherein the row selection means comprises switching means which is made conductive in response to a signal applied to the second row line connected to the selection transistor included in the memory cell.

Claim 30

A nonvolatile semiconductor memory device according to claim 17, wherein the insulation film is formed uniformly on the channel region.

Claim 31

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film formed between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate by utilizing a tunnel effect, and emitting electrons through the insulation film from the floating gate by utilizing a tunnel effect; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row lines and a selection transistor connected to one of the second row lines; column selection means for selecting one of the column lines in response to a column selection signal; first switching means connected between each of the second terminals of the memory cells and the reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data; and second switching means connected between the row selection means and the first row line, for controlling the first row line for selecting the cell transistor which is included in the memory cell including the selection transistor connected to the second row line, in response to a signal applied to the second row line connected to the selection transistor included in the memory cell.

Claim 32

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film formed between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate by utilizing a tunnel effect, and emitting electrons through the insulation film from the floating gate by utilizing a tunnel effect; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row lines and a selection transistor connected to one of the second row lines; column selection means for selecting one of the column lines in response to a column selection signal; first switching means connected between each of the second terminals of the memory cells and the reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data; and second switching means connected between the row selection means and the first row line, for controlling the first row line for selecting the cell transistor which is included in the memory cell including the selection transistor connected to the second row line, in response to a signal applied to the second row line connected to the selection transistor included in the memory cell.

Claim 33

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and a tunnel insulation film including a portion having a thickness sufficient to cause a tunnel effect between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the tunnel insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row lines and a selection transistor connected to one of the second row lines; column selection means for selecting one of the column lines in response to a column selection signal; first switching means connected between each of the second terminals of the memory cells and the reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data; and second switching means connected between the row selection means and the first row line, for controlling the first row line for selecting the cell transistor which is included in the memory cell including the selection transistor connected to the second row line, in response to a signal applied to the second row line connected to the selection transistor included in the same memory cell.

Claim 34

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and a tunnel insulation film including a portion having a thickness sufficient to cause a tunnel effect between the channel region and the floating gate, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column are commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the tunnel insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row lines and a selection transistor connected to one of the second row lines; column selection means for selecting one of the column lines in response to a column selection signal; first switching means connected between each of the second terminals of the memory cells and the reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data; and second switching means connected between the row selection means and the first row line, for controlling the first row line for selecting the cell transistor which is included in the memory cell including the selection transistor connected to the second row line, in response to a signal applied to the second row line connected to the selection transistor included in the same memory cell.

Claim 35

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film on the entire channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to one of the second row line; column selection means for selecting one of the column lines in response to a column selection signal; first switching means connected between each of the second terminals of the memory cells and the reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data; and second switching means connected between the row selection means and the first row line, for controlling the first row line for selecting the cell transistor which is included in the memory cell including the selection transistor connected to the second row line, in response to a signal applied to the second row line connected to the selection transistor included in the same memory cell.

Claim 36

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film on the entire channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means for selectively storing data into the cell transistors by one of injecting electrons through the insulation film into the floating gate, and emitting electrons through the insulation film from the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to one of the second row line; column selection means for selecting one of the column lines in response to a column selection signal; first switching means connected between each of the second terminals of the memory cells and the reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data; and second switching means connected between the row selection means and the first row line, for controlling the first row line for selecting the cell transistor which is included in the memory cell including the selection transistor connected to the second row line, in response to a signal applied to the second row line connected to the selection transistor included in the same memory cell.

Claim 37

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film formed between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of injecting electrons into the floating gate by setting the control gate at a potential higher than that of the channel region, thereby setting the floating gate at a potential higher than that of the channel region by utilizing capacitive coupling of the control gate and the floating gate, and emitting electrons from the floating gate by setting the control gate at a potential lower than that of the channel region, thereby setting the floating gate at a potential lower than that of the channel region by utilizing capacitive coupling of the control gate and the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to the second row line; column selection means for selecting one of the column lines in response to a column selection signal; first switching means connected between each of the second terminals of the memory cells and the reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data; and second switching means connected between the row selection means and the first row line, for controlling the first row line for selecting the cell transistor which is included in the memory cell including the selection transistor connected to the second row line, in response to a signal applied to the second row line connected to the selection transistor included in the same memory cell.

Claim 38

A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cells arranged in matrix form having first row lines, second row lines and column lines, each memory cell including cell transistors connected in series and a selection transistor for selecting the memory cell, and each of the cell transistors having a control gate, a floating gate, a channel region and an insulation film formed between the floating gate and the channel region, for electrically storing data by using charges stored in the floating gate, each memory cell having a first terminal and a second terminal, the first terminals of the memory cells in the same column being commonly connected to one of the column lines, the second terminals of the memory cells being connected to a reference potential, the control gates of the cell transistors in the same row being commonly connected to one of the first row lines, and the gate of the selection transistor being connected to one of the second row lines; data programming means connected to the first terminals of the memory cells, for selectively storing data into the cell transistors by one of injecting electrons into the floating gate by setting the control gate at a potential higher than that of the channel region, thereby setting the floating gate at a potential higher than that of the channel region by utilizing capacitive coupling of the control gate and the floating gate, and emitting electrons from the floating gate by setting the control gate at a potential lower than that of the channel region, thereby setting the floating gate at a potential lower than that of the channel region by utilizing capacitive coupling of the control gate and the floating gate; row selection means for selectively applying a signal to one of the first row lines and one of the second row lines in response to a row selection signal, thereby selecting a cell transistor connected to the first row line and a selection transistor connected to the second row line; column selection means for selecting one of the column lines in response to a column selection signal; first switching means connected between each of the second terminals of the memory cells and the reference potential, for disconnecting the memory cell from the reference potential when the data programming means stores data; and second switching means connected between the row selection means and the first row line, for controlling the first row line for selecting the cell transistor which is included in the memory cell including the selection transistor connected to the second row line, in response to a signal applied to the second row line connected to the selection transistor included in the same memory cell.

Claim 39

A nonvolatile semiconductor memory device according to claim 21, wherein the insulation film is formed uniformly on the channel region.

Claim 40

A nonvolatile semiconductor memory device according to any one of claims 19 to 23, wherein the second switching means is a MOS transistor, the source of the MOS transistor being connected to the row selection means, the drain of the MOS transistor being connected to the first row line, and the gate of the MOS transistor being connected to the second row line.

Claim 41

A nonvolatile semiconductor memory device according to any one of claims 19 to 23, wherein the second switching means is a MOS transistor, the drain of the MOS transistor being connected to the row selection means, the source of the MOS transistor being connected to the first row line, and the gate of the MOS transistor being connected to the second row line.