Semiconductor memory device having multi-gate transistors

Claim 1

A semiconductor memory device comprising; a first semiconductor region of one conductivity type; a plurality of memory transistors formed in said first semiconductor region and arranged in parallel with each other, each of said memory transistor including a pair of source and drain regions of an opposite conductivity type formed in a major surface of said first semiconductor region, a gate insulating layer formed on said major surface between said source and drain regions, a plurality of gate electrodes formed on said gate insulating layer and laterally separated from each other, and a plurality of opposite conductivity type regions formed in said first semiconductor region under the respective intervals between adjacent gate electrodes; an isolation region surrounding said first semiconductor region to prevent parasitic current flow to or from said first semiconductor region through said isolation region; a plurality of gate wiring layers provided to interconnect said gate electrodes of different transistors; and a plurality of switching transistors located outside said isolation region, each said switching transistor being electrically connected at its drain region to said source region of each said memory transistor, respectively.