US4580247A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor floating gate memory cell
Assignee: TDK Micronas GmbH
•
Filing: 1985-05-01
•
Granted: 1986-04-01
•
Expires: 2005-05-01
Abstract
Abstract A semiconductor memory cell includes a source-drain series connection of several memory transistors each comprising electrically floating gates and being of the depletion type, with a selection transistor being disposed between a first bit line and a second bit line. The memory cell remains programmable as long as one of the series-arranged memory transistors has an injector oxide free from defects. The memory transistors having an injector oxide damaged by a breakdown are not programmable but do not affect the programmability of the respective semiconductor memory cell.
Inventors
- 👤 Fritz G. Adam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:48
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
162 words
A semiconductor memory cell for use in a memory matrix said matrix including a first bit line, a second bit line, a programming line and a word line, said cell comprising: a serial branch between said first and second bit lines, said serial branch comprising a plurality of transistors having their source-drain regions connected in series and including at least a selection transistor and first and second memory transistors; a first floating gate extending throughout the channel region of said first memory transistors; a first charge injector for recharging said first floating gate; a first programming gate capacitively coupled to said first floating gate; a second floating gate extending throughout the channel region of said second memory transistor; a second charge injector for recharging said second floating gate; a second programming gate capacitively coupled to said second floating gate; said first and second programming gates being coupled to said programming line; and said selection transistor having its gate connected to said word.
Claim 2
Dependent Claim
162 words
A semiconductor memory cell for use in a memory matrix said matrix including a first bit line, a second bit line, a programming line and a word line, said cell comprising: a serial branch between said first and second bit lines, said serial branch comprising a plurality of transistors having their source-drain regions connected in series and including at least a selection transistor and first and second memory transistors; a first floating gate extending throughout the channel region of said first memory transistors; a first charge injector for recharging said first floating gate; a first programming gate capacitively coupled to said first floating gate; a second floating gate extending throughout the channel region of said second memory transistor; a second charge injector for recharging said second floating gate; a second programming gate capacitively coupled to said second floating gate; said first and second programming gates being coupled to said programming line; and said selection transistor having its gate connected to said word.
Claim 3
Dependent Claim
24 words
A semiconductor memory cell in accordance with claim 1 comprising: an injector selection transistor for selecting said first and second injectors of said cell.
Claim 4
Dependent Claim
23 words
A semiconductor memory cell in accordance with claim 2 wherein said injector selection transistor has its gate electrode coupled to said word line.
Claim 5
Dependent Claim
34 words
A semiconductor memory cell in accordance with claim 3 wherein said first and second injectors are connected in series and are separated from said memory transistors by a relatively narrow strip of field oxide.
Claim 6
Dependent Claim
165 words
A semiconductor memory comprising: a plurality of memory cells arranged cell for in a memory matrix; a first bit line; a second bit line; a programming line; and a word line; said cell comprising: a serial branch between said first and second bit lines, said serial branch comprising a plurality of transistors having their source-drain regions connected in series and including at least a selection transistor and first and second memory transistors; a first floating gate extending throughout the channel region of said first memory transistors; a first charge injector for recharging said first floating gate; a first programming gate capacitively coupled to said first floating gate; a second floating gate extending throughout the channel region of said second memory transistor; a second charge injector for recharging said second floating gate; a second programming gate capacitively coupled to said second floating gate; said first and second programming gates being coupled to said programming line; and said selection transistor having its gate connected to said word.
Claim 7
Dependent Claim
165 words
A semiconductor memory comprising: a plurality of memory cells arranged cell for in a memory matrix; a first bit line; a second bit line; a programming line; and a word line; said cell comprising: a serial branch between said first and second bit lines, said serial branch comprising a plurality of transistors having their source-drain regions connected in series and including at least a selection transistor and first and second memory transistors; a first floating gate extending throughout the channel region of said first memory transistors; a first charge injector for recharging said first floating gate; a first programming gate capacitively coupled to said first floating gate; a second floating gate extending throughout the channel region of said second memory transistor; a second charge injector for recharging said second floating gate; a second programming gate capacitively coupled to said second floating gate; said first and second programming gates being coupled to said programming line; and said selection transistor having its gate connected to said word.
Claim 8
Dependent Claim
24 words
A semiconductor memory cell in accordance with claim 5 comprising: an injector selection transistor for selecting said first and second injectors of said cell.
Claim 9
Dependent Claim
23 words
A semiconductor memory cell in accordance with claim 6 wherein said injector selection transistor has its gate electrode coupled to said word line.
Claim 10
Dependent Claim
34 words
A semiconductor memory cell in accordance with claim 7 wherein said first and second injectors are connected in series and are separated from said memory transistors by a relatively narrow strip of field oxide.
References Cited (Backward Citations)
US4514830A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-31 | 1989-09-30 | 1990-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-31 | 1993-09-30 | 1994-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-31 | 1997-09-30 | 1998-04-01 | $7700.00 | Window Closed / Lapsed |