Non-velatile semiconductor memory

Abstract

Abstract PURPOSE:To increase the density of integration while improving the reliability by a method wherein at least two each of memory transistors comprising P channel MIS field effect transistor with floating gate are connected in series. CONSTITUTION:Within P channel MIS field effect transistors Ml1n, Ml2n, Ml3n, Ml4n, the transistor Ml1n at the top step is connected to a digit line Dn through the intermediary of a select transistor Sln while another transistor Ml4n at the bottom step is connected to a VSS line. A word line Wlm is connected to the gates of transistors Mlm1, Mlm2. A memory transistor group is composed of the transistors Ml1n-Ml4n connected in series. Through these procedures, a non- volatile semiconductor memory with high reliability and integration as well as assured large capacity may be produced without fail.

Inventors

• 👤 Naotaka Sumihiro
• 👤 住廣　直孝

Bibliographic Details