Patent US5114530A successfully refreshed from Google Patents.
US5114530A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlevel dielectric process
Assignee: Texas Instruments Inc
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Filing: 1990-07-16
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Granted: 1992-05-19
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Expires: 2010-07-16
Abstract
Abstract A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.
Inventors
- 👤 Kalipatnam V. Rao
- 👤 Allan T. Mitchell
- 👤 James L. Paterson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 13:13
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; Y; Y10; Y10S; Y10S438/00; Y10S438/978
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
149 words
A method for fabricating an integrated circuit on a substrate having topographical features including at least two closely adjacent raised areas defining a low area therebetween, comprising the steps of: depositing a dielectric layer over the surface of said substrate so as to fill said defined low area to a thickness greater than a selected thickness and to cover said raised areas to a thickness greater than said selected thickness; anisotropically etching said dielectric layer such that the thickness of said dielectric layer covering at least one of said raised areas is reduced to a thickness equal to said selected thickness, and the thickness of said dielectric layer covering said defined low area remains greater than said selected thickness; removing selected portions of said dielectric layer to provide vias; and depositing and patterning a conductive layer, said conductive layer extending into said vias to contact components in said substrate.
Claim 2
Independent Claim
149 words
A method for fabricating an integrated circuit on a substrate having topographical features including at least two closely adjacent raised areas defining a low area therebetween, comprising the steps of: depositing a dielectric layer over the surface of said substrate so as to fill said defined low area to a thickness greater than a selected thickness and to cover said raised areas to a thickness greater than said selected thickness; anisotropically etching said dielectric layer such that the thickness of said dielectric layer covering at least one of said raised areas is reduced to a thickness equal to said selected thickness, and the thickness of said dielectric layer covering said defined low area remains greater than said selected thickness; removing selected portions of said dielectric layer to provide vias; and depositing and patterning a conductive layer, said conductive layer extending into said vias to contact components in said substrate.
Claim 3
Dependent Claim
13 words
A method as claimed in claim 1 wherein said substrate comprises crystalline silicon.
Claim 4
Dependent Claim
16 words
A method as in claim 1 wherein said dielectric layer is deposited conformally on said substrate.
Claim 5
Dependent Claim
24 words
A method as in claim 1 wherein said dielectric layer is selected from the group of silicate glasses, organic dielectrics and silicone polymer dielectrics.
Claim 6
Dependent Claim
12 words
A method as in claim 1 wherein said conductive layer comprises aluminum.
Claim 7
Dependent Claim
16 words
The method of claim 1 wherein said anisotropically etching step does not penetrate said dielectric layer.
Claim 8
Independent Claim
129 words
A method for fabricating an integrated circuit on a substrate having topographical features including at least two closely adjacent raised areas defining a low area therebetween, comprising the steps of: depositing a dielectric layer over the surface of said substrate so as to fill said defined low area to a thickness greater than a selected thickness and to cover said raised areas to a thickness greater than said selected thickness; and anisotropically etching said dielectric layer such that the thickness of said dielectric layer covering at least one of said raised areas is reduced to a thickness equal to said selected thickness, and the thickness of said dielectric layer covering said defined low area remains greater than said selected thickness and continues to substantially fill said defined low areas.
Claim 9
Independent Claim
129 words
A method for fabricating an integrated circuit on a substrate having topographical features including at least two closely adjacent raised areas defining a low area therebetween, comprising the steps of: depositing a dielectric layer over the surface of said substrate so as to fill said defined low area to a thickness greater than a selected thickness and to cover said raised areas to a thickness greater than said selected thickness; and anisotropically etching said dielectric layer such that the thickness of said dielectric layer covering at least one of said raised areas is reduced to a thickness equal to said selected thickness, and the thickness of said dielectric layer covering said defined low area remains greater than said selected thickness and continues to substantially fill said defined low areas.
Claim 10
Dependent Claim
18 words
The method of claim 7 and further comprising removing selected portions of said dielectric layer to provide vias.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |