Patent US5113087A successfully refreshed from Google Patents.
US5113087A
Expired / Lapsed
US
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Output circuit
Assignee: Toshiba Corp
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Filing: 1991-06-26
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Granted: 1992-05-12
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Expires: 2011-06-26
Abstract
Abstract An output circuit for obtaining stable rising and falling characteristics regardless of variations in threshold voltages of output transistors. The output circuit obtains such favorable characteristics by using input signals changing in a complementary manner, a first MOS transistor which outputs a high potential level signal in response to a drive signal, and an output terminal for receiving the high potential level signal. In addition, the output circuit contains a drain-current control connected to a gate-source path for maintaining a drain current at a predetermined value, a second MOS transistor connected to a gate-source path which sets the output terminal at a ground level when it is turned on, and a second drain current control connected to a gate source of the second MOS transistor for maintaining a drain current at a predetermined value.
Inventors
- 👤 Masaji Ueno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:21
CPC Classifications
H; H03; H03K; H03K17/00; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/003; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
268 words
An output circuit comprising: input signal supply means for simultaneously outputting first and second signals from two output nodes, said first and second signals having different levels which change in a complementary manner; first and second switching means which are turned on and off in a complementary manner upon receipt of the first and second signals, respectively, supplied from said input signal supply means; first level shift means connected between said first switching means, and a high potential level, for outputting a first drive signal when said first switching means is turned on upon receipt of the first signal; first MOS transistor having a drain coupled to said high potential level, and a gate coupled to receive the first drive signal supplied from said first level shift means; an output terminal coupled to a source of said first MOS transistor; first drain-current control means connected between said gate-source path of said first MOS transistor, for maintaining a drain current of said first MOS transistor at a predetermined value; second level shift means connected between said second switching means and said high potential level, for outputting a second drive signal when said second switching means is turned on upon receipt of the second signal; second MOS transistor having a gate coupled to receive the second drive signal supplied from said second level shift means, and having a drain and source respectively connected to said output terminal and a ground level; and second drain current control means connected between said gate-source of said second MOS transistor, for maintaining a drain current of said second MOS transistor at a predetermined value.
Claim 2
Dependent Claim
268 words
An output circuit comprising: input signal supply means for simultaneously outputting first and second signals from two output nodes, said first and second signals having different levels which change in a complementary manner; first and second switching means which are turned on and off in a complementary manner upon receipt of the first and second signals, respectively, supplied from said input signal supply means; first level shift means connected between said first switching means, and a high potential level, for outputting a first drive signal when said first switching means is turned on upon receipt of the first signal; first MOS transistor having a drain coupled to said high potential level, and a gate coupled to receive the first drive signal supplied from said first level shift means; an output terminal coupled to a source of said first MOS transistor; first drain-current control means connected between said gate-source path of said first MOS transistor, for maintaining a drain current of said first MOS transistor at a predetermined value; second level shift means connected between said second switching means and said high potential level, for outputting a second drive signal when said second switching means is turned on upon receipt of the second signal; second MOS transistor having a gate coupled to receive the second drive signal supplied from said second level shift means, and having a drain and source respectively connected to said output terminal and a ground level; and second drain current control means connected between said gate-source of said second MOS transistor, for maintaining a drain current of said second MOS transistor at a predetermined value.
Claim 3
Dependent Claim
20 words
A circuit according to claim 1, wherein said first and second level shift means are high breakdown voltage bipolar transistors.
Claim 4
Dependent Claim
22 words
A circuit according to claim 1, wherein said first and second level shift means are high breakdown voltage MOS field effect transistors.
Claim 5
Dependent Claim
19 words
The circuit according to claim 1, wherein said input signal supply means comprises an input terminal and an inverter.
Claim 6
Dependent Claim
16 words
The circuit according to claim 1, wherein said first and second switching means are MOS transistors.
Claim 7
Dependent Claim
61 words
The circuit according to claim 1, wherein said first drain current control means comprises third MOS transistor, a drain and gate of which are connected to the gate of said first MOS transistor and said first level shift means, and a plurality of diodes arranged between a source of said third MOS transistor and the source of said first MOS transistor.
Claim 8
Dependent Claim
56 words
The circuit according to claim 1, wherein said second drain-current control means comprises fourth MOS transistor, a drain and gate of which are connected to the gate of said second MOS transistor and said second level shift means, and a plurality of diodes arranged between a source of said fourth MOS transistor and said ground potential.
Claim 9
Dependent Claim
73 words
The circuit according to claim 1, further comprising fifth MOS transistor, a gate of which is connected to said input signal supply means, a source of which is connected to said ground potential, and a drain of which is connected to the gate of said second MOS transistor and is turned on upon receipt of the first signal, thereby to discharge a parasitic capacitance of the gate-source path of said second MOS transistor.
Claim 10
Dependent Claim
23 words
The circuit according to claim 1, which further comprises a Zener diode connected between the gate and source of said first MOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-12 | 1995-11-11 | 1996-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-12 | 1999-11-11 | 2000-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-12 | 2003-11-11 | 2004-05-12 | $7700.00 | Window Closed / Lapsed |