US4855624A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low-power bipolar-CMOS interface circuit
Assignee: National Semiconductor Corp
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Filing: 1988-02-02
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Granted: 1989-08-08
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Expires: 2008-02-02
Abstract
Abstract A biCMOS interface circuit receives a plurality of incoming signals at a first level and supplies a plurality of output signals at a second level. The interface circuit establishes control voltages which are used to maintain an identical trip point in each of a plurality of translator circuits. Generally, the trip point is set at midway between the "high" and the "low" levels of the incoming logic signal. The control voltages assure reliable performance over a wide operating environment.
Inventors
- 👤 Robert A. Kertis
- 👤 Douglas D. Smith
- 👤 Terrance L. Bowman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:00
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0175; H03K19/017509; H03K19/017518; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; H03K19/003; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
172 words
An interface circuit comprising: at least one translator circuit for translating a first level signal to a second level signal, the translator circuit comprising a first plurality of transistors and having a plurality of nodes, the translator circuit including means for preventing current flow in the translator circuit when the second level signal is at a steady state high and low level; generator means for generating a desired trip point voltage; a simulated translator circuit connected between the translator circuit and the generator means to receive the desired trip point voltage and simulate one of the translator circuits, the simulated translator circuit comprising a second plurality of transistors having a plurality of nodes, each of the second plurality of transistors being biased to a particular bias level in response to the trip point voltage; connecting means for connecting at least one node in said simulated translator circuit to a corresponding node in the translator circuit to provide a control voltage bias signal to establish a desired trip point for the translator circuit.
Claim 2
Dependent Claim
172 words
An interface circuit comprising: at least one translator circuit for translating a first level signal to a second level signal, the translator circuit comprising a first plurality of transistors and having a plurality of nodes, the translator circuit including means for preventing current flow in the translator circuit when the second level signal is at a steady state high and low level; generator means for generating a desired trip point voltage; a simulated translator circuit connected between the translator circuit and the generator means to receive the desired trip point voltage and simulate one of the translator circuits, the simulated translator circuit comprising a second plurality of transistors having a plurality of nodes, each of the second plurality of transistors being biased to a particular bias level in response to the trip point voltage; connecting means for connecting at least one node in said simulated translator circuit to a corresponding node in the translator circuit to provide a control voltage bias signal to establish a desired trip point for the translator circuit.
Claim 3
Dependent Claim
19 words
A circuit as in claim 1 wherein the means for preventing includes a flip-flop in each said translator circuit.
Claim 4
Dependent Claim
30 words
A circuit as in claim 1 wherein each said translator circuit includes at least one transistor in series with a latch type flip-flop in series with a current source means.
Claim 5
Dependent Claim
24 words
An interface circuit as in claim 3 wherein said current source means are controlled by a control voltage bias signal from the simulated translator.
Claim 6
Dependent Claim
50 words
An interface circuit as in claim 3 wherein each said transistor in said translator circuit includes an input terminal and a plurality of output terminals, wherein at least one terminal on at least one said transistor is connected to receive a control voltage bias signal from the simulated translator circuit.
Claim 7
Dependent Claim
171 words
An interface circuit comprising: at least one translator circuit for translating an ECL level signal to a CMOS level signal, the translator circuit comprising a first plurality of transistors and having a plurality of nodes, and further having a trip point established by at least one control voltage bias signal; a trip point generator for providing a predetermined trip point voltage; a simulated translator circuit including a second plurality of transistors connected to simulate the translator circuit and having a plurality of nodes, the simulated translator coupled to receive said trip point voltage as an input signal; means for connecting at least one node in said simulated translator circuit to a corresponding node in each said translator circuit as a control voltage bias signal, establishing thereby identical trip points for the translator circuit and the simulated translator circuit; and means connected to each translator circuit for preventing flow of DC current in the translator circuit at steady state; whereby identical trip points are substantially equal to the predetermined trip point voltage.
Claim 8
Dependent Claim
171 words
An interface circuit comprising: at least one translator circuit for translating an ECL level signal to a CMOS level signal, the translator circuit comprising a first plurality of transistors and having a plurality of nodes, and further having a trip point established by at least one control voltage bias signal; a trip point generator for providing a predetermined trip point voltage; a simulated translator circuit including a second plurality of transistors connected to simulate the translator circuit and having a plurality of nodes, the simulated translator coupled to receive said trip point voltage as an input signal; means for connecting at least one node in said simulated translator circuit to a corresponding node in each said translator circuit as a control voltage bias signal, establishing thereby identical trip points for the translator circuit and the simulated translator circuit; and means connected to each translator circuit for preventing flow of DC current in the translator circuit at steady state; whereby identical trip points are substantially equal to the predetermined trip point voltage.
Claim 9
Dependent Claim
21 words
The interface circuit of claim 6, wherein the means for preventing includes a latch type flip-flop in each said translator circuit.
Claim 10
Dependent Claim
29 words
The interface circuit of claim 7, wherein each said translator includes at least one transistor in series with a latch type flip-flop in series with a current source means.
Claim 11
Dependent Claim
23 words
The interface circuit of claim 8, wherein said current source means are controlled by a control voltage bias signal from the simulated translator.
Claim 12
Dependent Claim
38 words
The interface circuit of claim 8, wherein said transistor includes an input terminal and a plurality of output terminals, at least one of said terminals being connected to a said control voltage bias signal from said simulated translator.
Claim 13
Dependent Claim
257 words
An interface circuit comprising in combination: at least one translator circuit for translating an ECL level signal to a CMOS level signal, each translator circuit comprising a first plurality of transistors and having a plurality of nodes, and further having a trip point established by at least one control voltage bias signal, each said translator including at least one transistor in series with a latch type flip-flop in series with a current source means, said current source means having an input terminal; a trip point generator for providing a predetermined trip point voltage; a simulated translator circuit comprising a second plurality of transistors connected to simulate one said translator circuit and having a plurality of nodes, each said transistor including an input terminal and a plurality of output terminals, said simulated translator coupled to receive said trip point voltage as an input; means for connecting at least one node in said simulated translator circuit to a corresponding node in each said translator circuit as a control voltage bias signal, establishing thereby identical trip points for each said translator circuit, the nodes selected including said input terminal of said current source means and at least one said terminal on at least one said transistor comprising each said translator circuit; means connected to each translator circuit for preventing the flow of DC current in each said translator circuit at steady state, the means for preventing includes a latch type flip-flop in each said translator circuit; whereby the identical trip points are substantially equal to the predetermined trip point voltage.
Claim 14
Dependent Claim
257 words
An interface circuit comprising in combination: at least one translator circuit for translating an ECL level signal to a CMOS level signal, each translator circuit comprising a first plurality of transistors and having a plurality of nodes, and further having a trip point established by at least one control voltage bias signal, each said translator including at least one transistor in series with a latch type flip-flop in series with a current source means, said current source means having an input terminal; a trip point generator for providing a predetermined trip point voltage; a simulated translator circuit comprising a second plurality of transistors connected to simulate one said translator circuit and having a plurality of nodes, each said transistor including an input terminal and a plurality of output terminals, said simulated translator coupled to receive said trip point voltage as an input; means for connecting at least one node in said simulated translator circuit to a corresponding node in each said translator circuit as a control voltage bias signal, establishing thereby identical trip points for each said translator circuit, the nodes selected including said input terminal of said current source means and at least one said terminal on at least one said transistor comprising each said translator circuit; means connected to each translator circuit for preventing the flow of DC current in each said translator circuit at steady state, the means for preventing includes a latch type flip-flop in each said translator circuit; whereby the identical trip points are substantially equal to the predetermined trip point voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-07 | 1993-02-06 | 1993-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-07 | 1997-02-06 | 1997-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-07 | 2001-02-06 | 2001-08-08 | $7700.00 | Window Closed / Lapsed |