US4645954A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ECL to FET interface circuit for field effect transistor arrays
Assignee: International Business Machines Corp
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Filing: 1985-10-21
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Granted: 1987-02-24
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Expires: 2005-10-21
Abstract
Abstract An interface circuit for coupling bipolar ECL logic circuit signals to an FET logic array. The interface receives chip select signals and their complement on a dual rail input line. A small signal amplifier comprising an FET amplifier having an input FET transistor connected through its source and gate to the dual rail input terminals, converts the chip enable signal to a high level clocking signal. An FET dynamic sense amplifier receives a bipolar ECL logic level to be converted to an FET logic level, and receives a reference level from the bipolar transistor logic circuit. Upon clocking of the dynamic sense amplifier by the small signal multiplier, the true and complementary FET logic levels corresponding to the input bipolar logic levels are provided by the dynamic sense amplifier.
Inventors
- 👤 Stanley E. Schuster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:50
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K3/356104; H03K3/356113
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
154 words
An interface circuit for driving an FET logic circuit from a bipolar transistor logic circuit comprising: dual rail input terminals for receiving complementary clocking logic levels from said bipolar transistor logic circuit; a small signal multiplier having an output and comprising an FET amplifier having an input FET transistor connected through its source and gate to said dual rail input terminals producing an FET logic level in response to said complementary clocking logic levels; and an FET dynamic sense amplifier having a first input connected to a reference voltage level provided by said bipolar transistor logic circuit, Vref, a second input connected to a logic output connection of said bipolar transistor logic circuit, ECL1 and a clocking input connected to said small signal multiplier output, said dynamic sense amplifier providing complementary FET logic levels which are determined by the difference of voltage potential between said first and second inputs of Vref and ECL1, respectively.
Claim 2
Dependent Claim
154 words
An interface circuit for driving an FET logic circuit from a bipolar transistor logic circuit comprising: dual rail input terminals for receiving complementary clocking logic levels from said bipolar transistor logic circuit; a small signal multiplier having an output and comprising an FET amplifier having an input FET transistor connected through its source and gate to said dual rail input terminals producing an FET logic level in response to said complementary clocking logic levels; and an FET dynamic sense amplifier having a first input connected to a reference voltage level provided by said bipolar transistor logic circuit, Vref, a second input connected to a logic output connection of said bipolar transistor logic circuit, ECL1 and a clocking input connected to said small signal multiplier output, said dynamic sense amplifier providing complementary FET logic levels which are determined by the difference of voltage potential between said first and second inputs of Vref and ECL1, respectively.
Claim 3
Dependent Claim
45 words
The interface circuit of claim 1 wherein said multiplier circuit input FET transistor has a dopant level which provides conduction threshold at substantially the voltage represented by the difference between said gate and source connections for one logic state on said dual rail input terminals.
Claim 4
Dependent Claim
130 words
The interface circuit of claim 1 wherein said sense amplifier includes a clocked differential latch having first and second input nodes and a clock input, said latch input nodes assuming states proportional to the difference between input node potentials when a clocking signal is received; first and second gate means, said first gate means connecting Vref to one of said nodes and said second gate means connecting ECL1 to the other of said nodes; means for enabling said first and second gate means in synchronism with said clocking signal, whereby said latch assumes a state proportional to the difference between said first and second input voltages; and, first and second inverter circuits connected to said nodes whereby first and second complementary outputs are provided representing logic levels at said nodes.
Claim 5
Dependent Claim
142 words
The interface circuit of claim 1 wherein said signal multiplier comprises: an input FET transistor of a first conductivity type having a source and gate connected to said rails, and a load FET transistor having a source and drain connected in series with said input transistor source and drain, and a gate connected to a common voltage connection; an amplifier stage including second and third FET transistors having gate connections connected to the junction of said serial connection of said input FET transistor and load transistor and having source and drain connections serially connected to form an output connection; and means for applying a DC voltage across said load transistor gate and drain connection and said amplifier serially connected transistors, whereby complementary input signals applied to said input FET transistor gate and source produce a single logic state at said output connection.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-23 | 1990-08-25 | 1991-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-23 | 1994-08-25 | 1995-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-23 | 1998-08-25 | 1999-02-24 | $7700.00 | Window Closed / Lapsed |