CMOS Address buffer circuit

Claim 1

An address buffer circuit for a semiconductor memory device or the like, comprising: a double cross-coupled CMOS bistable flip-flop circuit having a pair of N-channel driver transistors and a pair of P-channel load transistors, each N-channel transistor having a source-drain path in series with the source-drain path of the corresponding P-channel transistor, the drains of the N-channel transistors providing output nodes, with the gates of the N- and P-channel transistors on each side respectively coupled to the drain of the N-channel driver transistor of the other, a pair of P-channel input transistors, each having a souce-drain path in series between the source-drain path of one of said P-channel load transistors and a supply node, first and second N-channel gating transistors, the first gating transistor having a source-drain path connected between the gate of one of said pair of input transistors and an input node, the second transistor having a source-drain path connected between the gate of the other of said pair of input transistors and a reference voltage, a P-channel supply transistor having a source-drain path connected between said supply node and a voltage supply, and a single activating clock voltage connected in common to the gates of said first and second gating transistors and to the gate of said supply transistor.