US4812683A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit connecting input and output signal leads
Assignee: Gazelle Microcircuits Inc
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Filing: 1987-05-19
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Granted: 1989-03-14
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Expires: 2007-05-19
Abstract
Abstract This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.
Inventors
- 👤 Mark E. Fitzpatrick
- 👤 Andrew C. Graham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:03
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/023; H03K3/0231; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K19/0952; H03K3/353; H03K3/356; H03K3/3565
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
188 words
A logic circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising: first and second transistors; said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal; load means connected between the first voltage supply terminal and the first current handling terminal of the first transistor; said second transistor having a first current handling terminal connected to the first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal; a first load device connected between the second current handling terminal of the second transistor and the second voltage supply terminal; the control terminal of the first transistor being connected to the input signal lead; a second load device connected between the second current handling terminal of the second transistor and the output signal lead; and a third load device connected between the second current handling terminal of the first transistor and the second voltage supply terminal.
Claim 2
Dependent Claim
188 words
A logic circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising: first and second transistors; said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal; load means connected between the first voltage supply terminal and the first current handling terminal of the first transistor; said second transistor having a first current handling terminal connected to the first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal; a first load device connected between the second current handling terminal of the second transistor and the second voltage supply terminal; the control terminal of the first transistor being connected to the input signal lead; a second load device connected between the second current handling terminal of the second transistor and the output signal lead; and a third load device connected between the second current handling terminal of the first transistor and the second voltage supply terminal.
Claim 3
Dependent Claim
54 words
The structure as in claim 1 wherein the first load device is a third transistor having a first current handling terminal connected to the output signal lead, a control terminal connected to the second current handling terminal of the first transistor, and a second current handling terminal connected to the second voltage supply terminal.
Claim 4
Dependent Claim
31 words
The structure as in claim 2 wherein said third load device comprises a diode forward biased in the direction from the first voltage supply terminal to the second voltage supply terminal.
Claim 5
Dependent Claim
31 words
The structure as in claim 2 wherein said second load device comprises a diode forward biased in the direction from the first voltage supply terminal to the second voltage supply terminal.
Claim 6
Dependent Claim
31 words
The structure as in claim 4 wherein the third load device comprises a diode forward biased in the direction from the first voltage supply terminal to the second voltage supply terminal.
Claim 7
Dependent Claim
17 words
The structure as in claim 2 wherein the second voltage supply terminal is a ground supply terminal.
Claim 8
Dependent Claim
78 words
The structure as in claim 2 and further having an additional input signal lead for receiving an additional input signal, and further comprising a fourth transistor having a first current handling terminal connected to the first current handling terminal of the first transistor, a second current handling terminal connected to the second current handling terminal of the first transistor, and a control terminal, the additional input signal lead being connected to the control terminal of the fourth transistor.
Claim 9
Dependent Claim
289 words
A logic circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising: first, second and third transistors: said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal connected to the second voltage supply terminal: load means connected between the first voltage supply terminal and the first current handling terminal of the first transistor: said second transistor having a first current handling terminal connected to said first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal: said third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal connected to the second voltage supply terminal: the control terminals of the first and third transistors being connected to the input signal lead: the output signal lead being connected to the first current handling terminal of the third transistor: a fourth transistor having a first current handling terminal connected to the first current handling terminal of the first transistor, a control terminal, and a second current handling terminal connected to the second current handling terminal of the first transistor: a fifth transistor having a first current handling terminal connected to the first current handling terminal of the third transistor, a control terminal, and a second current handling terminal connected to the second current handling terminal of the third transistor, and a second input signal lead for receiving an input signal, connected to the control terminals of the fourth and fifth transistors.
Claim 10
Dependent Claim
289 words
A logic circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising: first, second and third transistors: said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal connected to the second voltage supply terminal: load means connected between the first voltage supply terminal and the first current handling terminal of the first transistor: said second transistor having a first current handling terminal connected to said first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal: said third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal connected to the second voltage supply terminal: the control terminals of the first and third transistors being connected to the input signal lead: the output signal lead being connected to the first current handling terminal of the third transistor: a fourth transistor having a first current handling terminal connected to the first current handling terminal of the first transistor, a control terminal, and a second current handling terminal connected to the second current handling terminal of the first transistor: a fifth transistor having a first current handling terminal connected to the first current handling terminal of the third transistor, a control terminal, and a second current handling terminal connected to the second current handling terminal of the third transistor, and a second input signal lead for receiving an input signal, connected to the control terminals of the fourth and fifth transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |