EP0068884A2
Expired / Lapsed
EP
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An output circuit of a semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1982-06-29
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Granted: —
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Expires: 2002-06-29
Abstract
Abstract An output circuit (OB) of a semiconductor device for suppressing erroneous operation due to potential variations of the power supply line or the ground line. The output circuit comprises an output stage inverter (T 5 , T 6 ) connected between the power supply line (V cc ) and the ground line (V ss ) and a clamping circuit (CL 1 , CL 2 , CL 3 ) for clamping the voltages applied to the output stage inverter (T 5 , T 6 ). An instantaneous large current which flows through the output stage inverter (T 5 , T 6 ) during transition of its state is greatly suppressed so that erroneous operation is prevented.
Inventors
- 👤 Mitsuo Higuchi
- 👤 Masanobu Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 16:43
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315; H03K19/00369; H03K19/00384; H03K5/00; H03K5/01; H03K5/02; H03K5/023; G11C2207/00; G11C2207/10; G11C2207/108
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
119 words
An output circuit of a semiconductor device, comprising: a first MIS transistor and a second MIS transistor connected in series between a power supply line and a ground line, said first and said second MIS transistors having gates operatively receiving a first signal and a second signal, respectively, said first and said second MIS transistors being turned on and off or being turned off and on, respectively, in response to a high--potential level or a low-potential level of said first and said second signals; an output terminal connected to a connecting point of said first and said second MOS transistors; and a clamping circuit for clamping the potentials of said first and said second signals within a predetermined level.
Claim 2
Dependent Claim
119 words
An output circuit of a semiconductor device, comprising: a first MIS transistor and a second MIS transistor connected in series between a power supply line and a ground line, said first and said second MIS transistors having gates operatively receiving a first signal and a second signal, respectively, said first and said second MIS transistors being turned on and off or being turned off and on, respectively, in response to a high--potential level or a low-potential level of said first and said second signals; an output terminal connected to a connecting point of said first and said second MOS transistors; and a clamping circuit for clamping the potentials of said first and said second signals within a predetermined level.
Claim 3
Dependent Claim
83 words
An output circuit as set forth in claim 1, wherein said clamping circuit comprises a means for clamping the high-potential level of said first signal and said second signal to a level lower than at least a predetermined level of said power supply line so that said high-potential level of said first signal and said second signal is prevented from becoming a level higher than said predetermined level of said power supply line even when the potential of said power supply line varies.
Claim 4
Dependent Claim
80 words
An output circuit as set forth in claim 1, wherein said clamping circuit comprises a means for clamping the low-potential level of said first signal and said second signal to a level higher than at least a predetermined level of said ground line so that said low-potential level of said first signal and said second signal is prevented from becoming a level lower than a predetermined level of said ground line even when the potential of said ground line varies.
Claim 5
Dependent Claim
65 words
An output circuit as set forth in claim 1, wherein said clamping circuit comprises a first-signal clamping means which includes a plurality of diodes connected in series between the gate of said first MIS transistor and said ground line and a second-signal clamping means which includes a plurality of diodes connected in series between the gate of said second MIS transistor and said ground line.
Claim 6
Dependent Claim
26 words
An output circuit as set forth in claim 1, wherein said clamping circuit comprises a means for directly clamping the potential of said power supply line.
Claim 7
Dependent Claim
82 words
An output circuit as set forth in claim 5, wherein said means for directly clamping the potential of said power supply line comprises a third MIS transistor connected between said power supply line and said first or second MIS transistor, and an inverter having an input and an output, said input of said inverter operatively receiving a voltage proportional to the voltage of said power supply and said output of said inverter being connected to the gate of said third MIS transistor.
Claim 8
Dependent Claim
27 words
An output circuit as set forth in any one of claims 1 through 6, wherein said first and said second MIS transistors constitute an enhancement-type N-MOS inverter.
Claim 9
Dependent Claim
29 words
An output circuit as set forth in any one of claims 1, 2, 3, 5, or 6, wherein said first and said second MIS transistors constitute a C-MOS inverter.
References Cited (Backward Citations)
No citation records indexed.
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