US5089726A
Expired / Lapsed
US
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Fast cycle time clocked amplifier
Assignee: International Business Machines Corp
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Filing: 1990-11-29
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Granted: 1992-02-18
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Expires: 2010-11-29
Abstract
Abstract A circuit incorporating a clocked first stage and unlocked second and third stages with amplification for driving capacitance loads with the output nodes each coupling its changed state back to the earlier stages to reset them independent of the clock. The circuit may use complementary metal-oxide semiconductor devices of various gate widths.
Inventors
- 👤 Barbara A. Chappell
- 👤 Terry I. Chappell
- 👤 Stanley E. Schuster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:53
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356069; H03K3/356017; H03K3/356104; H03K3/356113
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
299 words
A circuit for amplifying an input signal comprising: a first transistor having a first terminal adapted for coupling to a first voltage supply, a second terminal coupled to a first output node and a third terminal adapted for coupling to said input signal, a second transistor having a fourth terminal adapted for coupling to said first voltage supply, a fifth terminal coupled to a second output node and a sixth terminal adapted for coupling to a reference signal, first and second means for supplying current to said first and second output nodes, respectively, third means adapted for coupling to a clock signal for presetting the voltage of said first and second output nodes to a second voltage at first times and for disabling said third means at second times in response to said clock signal whereby at second times said first and second output nodes respond to said input signal, said first output node coupled through a first and second inverter to a third output node, said second output node coupled through a third and fourth inverter to a fourth output node, fourth means coupled to said third output node and to said first output node for resetting after a predetermined first delay the voltage of said first output node to said second voltage at times said third output node goes to a fourth voltage from a third voltage, and fifth means coupled to said fourth output node and to said second output node for resetting after a predetermined second delay the voltage of said second node to said second voltage at times said fourth output node goes to a fourth voltage from a third voltage, whereby a changed output state generates a signal to reset the voltage of the changed nodes of the circuit to reduce cycle time.
Claim 2
Dependent Claim
299 words
A circuit for amplifying an input signal comprising: a first transistor having a first terminal adapted for coupling to a first voltage supply, a second terminal coupled to a first output node and a third terminal adapted for coupling to said input signal, a second transistor having a fourth terminal adapted for coupling to said first voltage supply, a fifth terminal coupled to a second output node and a sixth terminal adapted for coupling to a reference signal, first and second means for supplying current to said first and second output nodes, respectively, third means adapted for coupling to a clock signal for presetting the voltage of said first and second output nodes to a second voltage at first times and for disabling said third means at second times in response to said clock signal whereby at second times said first and second output nodes respond to said input signal, said first output node coupled through a first and second inverter to a third output node, said second output node coupled through a third and fourth inverter to a fourth output node, fourth means coupled to said third output node and to said first output node for resetting after a predetermined first delay the voltage of said first output node to said second voltage at times said third output node goes to a fourth voltage from a third voltage, and fifth means coupled to said fourth output node and to said second output node for resetting after a predetermined second delay the voltage of said second node to said second voltage at times said fourth output node goes to a fourth voltage from a third voltage, whereby a changed output state generates a signal to reset the voltage of the changed nodes of the circuit to reduce cycle time.
Claim 3
Dependent Claim
14 words
The circuit of claim 1 wherein said first transistor is a field effect transistor.
Claim 4
Dependent Claim
25 words
The circuit of claim 2 wherein said first terminal is the source, said second terminal is the drain and said third terminal is the gate.
Claim 5
Dependent Claim
14 words
The circuit of claim 2 wherein said second transistor is a field effect transistor.
Claim 6
Dependent Claim
25 words
The circuit of claim 4 wherein said fourth terminal is the source, said fifth terminal is the drain and said sixth terminal is the gate.
Claim 7
Dependent Claim
17 words
The circuit of claim 1 wherein said first and second transistors are n channel field effect transistors.
Claim 8
Dependent Claim
40 words
The circuit of claim 4 wherein said first means includes a third field-effect transistor having its gate coupled to said second output node, its drain coupled to said first output node and its source coupled to a source of current.
Claim 9
Dependent Claim
40 words
The circuit of claim 7 wherein said second means includes a fourth field-effect transistor having its gate coupled to said first output node, its drain coupled to said second output node and its source coupled to a source of current.
Claim 10
Dependent Claim
42 words
The circuit of claim 4 wherein said first means for supplying current includes a third field-effect transistor having its gate coupled to said clock signal, its source coupled to a source of current and its drain coupled to said first output node.
Claim 11
Dependent Claim
44 words
The circuit of claim 8 wherein said first means includes a fifth field-effect transistor having its gate coupled to said clock signal, its source coupled to a source of current and its drain coupled to said sources of said third and fourth field-effect transistors.
Claim 12
Dependent Claim
37 words
The circuit of claim 4 wherein said third means includes a third and fourth field-effect transistors having their source coupled to said first and second nodes respectively and their gate adapted for coupling to said clock signal.
Claim 13
Dependent Claim
35 words
The circuit of claim 1 wherein said first inverter includes a p channel transistor having a first conductivity in series with an n channel transistor having a conductivity greater than 5 times said first conductivity.
Claim 14
Dependent Claim
35 words
The circuit of claim 1 wherein said second inverter includes an n channel transistor having a first conductivity in series with a p channel transistor having a conductivity greater than 5 times said first conductivity.
Claim 15
Dependent Claim
27 words
The circuit of claim 1 wherein said first inverter includes a third transistor having a first conductivity greater than 3 times the conductivity of said first transistor.
Claim 16
Dependent Claim
30 words
The circuit of claim 14 wherein said second inverter includes a fourth transistor having a conductivity greater than 3 times the conductivity of said third transistor of said first inverter.
Claim 17
Dependent Claim
37 words
The circuit of claim 1 wherein said fourth means includes a third transistor having its drain coupled to said first node, its gate coupled to said third node, and its source coupled to said first voltage supply.
Claim 18
Dependent Claim
41 words
The circuit of claim 1 wherein said fourth means includes fifth and sixth inverters coupled in series to the gate of a third transistor having its drain coupled to said first node and its source coupled to said first voltage supply.
Claim 19
Dependent Claim
19 words
The circuit of claim 1 wherein said fourth means includes a transmission line to provide a fixed time delay.
Claim 20
Dependent Claim
41 words
The circuit of claim 17 wherein said fifth means includes seventh and eighth inverters coupled in series to the gate of a fourth transistor having its drain coupled to said second node and its source coupled to said first voltage supply.
Claim 21
Dependent Claim
37 words
The circuit of claim 17 wherein said fifth means includes a fourth transistor having its drain coupled to said second node, its gate coupled to said fourth node, and its source coupled to said first voltage supply.
Claim 22
Dependent Claim
41 words
The circuit of claim 1 wherein said fifth means includes fifth and sixth inverters coupled in series to the gate of a third transistor having its drain coupled to said second node and its source coupled to said first voltage supply.
Claim 23
Dependent Claim
37 words
The circuit of claim 1 wherein said fifth means includes a third transistor having its drain coupled to said second node, its gate coupled to said fourth node, and its source coupled to said first voltage supply.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |