Sense amplifier

Claim 2

A sense amplifier coupled to a plurality of MOS memory cells, each providing a different differential signal, and to first and second power supplies, said sense amplifier comprising: first and second bipolar transistors having current paths connected together at a first end and having bases coupled to receive a differential signal from one of said plurality of MOS memory cells; first and second load elements each connected between said first power supply and a second end of a different one of said bipolar transistor current paths; a constant current source connected between said second power supply and said first ends of said bipolar transistor current paths; first and second MOS transistors each having a gate coupled to a different one of said second ends of said first and second bipolar transistor current paths, said first and second MOS transistors having current paths connected at a first end to said second power supply; and a current mirror circuit, including a third MOS transistor, said current mirror circuit being connected to a second end of said first and second MOS transistor current paths to supply a constant current to said first and second MOS transistors, and said third MOS transistor receiving a signal from said second end of said first MOS transistor current path.

Claim 3

The sense amplifier according to claim 1 wherein said load elements each includes a resistor.

Claim 4

The sense amplifier according to claim 1 further comprising a CMOS inverter coupled to said second end of one of said first and second MOS transistor current paths.

Claim 5

The sense amplifier according to claim 1 wherein each of said first and second bipolar transistors includes a Darlington transistor pair.

Claim 6

A sense amplifier responsive to a chip enable signal and coupled to a plurality of MOS transistor type memory cells each providing a different differential signal and to first and second power supplies, said sense amplifier comprising: first and second bipolar transistors having current paths connected at a first end to said first power supply and having bases coupled to receive a differential signal from one of said memory cells; first and second MOS transistors each having a current path coupled at a first end to said second power supply and at a second end to a second end of a different one of said first and second bipolar transistor current paths, said first and second MOS transistors each having a gate coupled to said chip enable signal for controlling the conductivity state of said first and second MOS transistors; third and fourth bipolar fransistors each being connected to a different one of said first and second bipolar transistors in a Darlington pair configuration, said third and fourth bipolar transistors having current paths connected together at first ends; first and second load elements each connected between said first power supply and a second end of a different one of said third and fourth bipolar transistor current paths; a constant current source connected between said first ends of said third and fourth bipolar transistor current paths and said second power supply; third and fourth MOS transistors each having a gate coupled to said second end of a different one of said third and fourth bipolar transistor current paths, said third and fourth MOS transistors each having a current path with a first end connected to said second power supply; and a current mirror circuit formed of MOS transistors and connected between a second end of said current paths of said third and fourth transistors and said second power supply, thereby supplying said third and fourth MOS transistors with a constant current, and said mirror circuit receiving a signal from said second end of said third MOS transistor current paths.

Claim 7

A sense amplifier responsive to a chip enable signal and coupled to a plurality of MOS transistor type memory cells each providing a different differential signal and to first and second power supplies, said sense amplifier comprising: first and second bipolar transistors having current paths connected at a first end to said first power supply and having bases coupled to receive a differential signal from one of said memory cells; first and second MOS transistors each having a current path coupled at a first end to said second power supply and at a second end to a second end of a different one of said first and second bipolar transistor current paths, said first and second MOS transistors each having a gate coupled to said chip enable signal for controlling the conductivity state of said first and second MOS transistors; third and fourth bipolar fransistors each being connected to a different one of said first and second bipolar transistors in a Darlington pair configuration, said third and fourth bipolar transistors having current paths connected together at first ends; first and second load elements each connected between said first power supply and a second end of a different one of said third and fourth bipolar transistor current paths; a constant current source connected between said first ends of said third and fourth bipolar transistor current paths and said second power supply; third and fourth MOS transistors each having a gate coupled to said second end of a different one of said third and fourth bipolar transistor current paths, said third and fourth MOS transistors each having a current path with a first end connected to said second power supply; and a current mirror circuit formed of MOS transistors and connected between a second end of said current paths of said third and fourth transistors and said second power supply, thereby supplying said third and fourth MOS transistors with a constant current, and said mirror circuit receiving a signal from said second end of said third MOS transistor current paths.

Claim 8

The sense amplifier according to claim 5 wherein said load elements each includes a resistor.

Claim 9

The sense amplifier according to claim 5 wherein said constant current source includes: a signal level converter receiving said chip enable signal at MOS signal levels and outputting an enable signal at TTL levels; a fifth bipolar transistor having a current path with a first end connected to said first ends of said third and fourth bipolar transistor current paths, and having a gate receiving said enable signal from said signal level converter; and a third load element connected between a second end of said fifth bipolar transistor current path and said second power source.

Claim 10

The sense amplifier according to claim 7 wherein said signal level converter includes: an inverter receiving said chip enable signal at MOS signal levels and having an output terminal; a fifth MOS transistor of a first conductivity type having a gate electrode connected to said output terminal of said inverter; a first resistor connected between a first end of a current path of said fifth MOS transistor and said first power supply; a sixth MOS transistor of a second conductivity type connected between a second end of said fifth MOS transistor current path and said second power supply, and having a gate connected to said inverter output terminal; a sixth bipolar transistor having a current path with a first end connected to said first power supply and a base connected to said second end of said fifth MOS transistor current path; second and third resistors connected in series between a second end of said sixth bipolar transistor current path and said second power supply; and a seventh bipolar transistor having a current path connected in parallel with said current path of said sixth MOS transistor, and having a base connected to a node between said second and third resistors, whereby an enable signal with TTL signal levels is obtained from said second end of said sixth bipolar transistor current path.

Claim 11

The sense amplifier according to claim 5 further comprising a CMOS inverter for receiving and inverting a signal from said second end of one of said third and fourth MOS transistors.

Claim 12

The sense amplifier according to claim 13 further comprising a first resistor connected between said second power supply and said first end of said first MOS transistor current path, and a second resistor coupled between said second power supply and said first end of said second MOS transistor current path.