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US3760194A Expired / Lapsed US ⏱️ 0.0 years remaining

High speed sense amplifier

Assignee: Advanced Mamory Systems
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Filing: 1972-01-31
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Granted: 1973-09-18
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Expires: 1992-01-31
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Abstract

Abstract A high speed sense amplifier particularly suited for use with ECL compatible integrated memory components. The sense amplifier is basically a two-stage amplifier having an input stage and an output stage. The input stage is a low input impedance differential current amplifier and the output stage is a differentially driven current switch typically coupled to a standard single ended ECL emitter follower output. The differential current amplifier used for the input stage responds to a low input current. The response time of the amplifier is short even in the presence of relatively high capacitance at the input terminals due to the circuitry connected thereto.

Inventors

  • 👤 R Lutz
  • 👤 J Bernacchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 08:21
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416; G11C7/00; G11C7/06; G11C7/062; G11C7/065

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 203 words
A sense amplifier for high speed memory applications comprising an input stage having first, second, third and fourth transistors of the same conductivity type, and an output stage, said first and second transistors having their bases coupled together and to a first power supply terminal and having their collectors coupled through first and second resistors, respectively, in said output stage to a second power supply terminal, said collector of said first transistor further being coupled to the collector of said third transistor and said collector of said second transistor being coupled to the collector of said fourth transistor, the emitter of said first transistor being coupled to the base of said fourth transistor, to a first input terminal, and to a first current source, the emitter of said second transistor being coupled to the base of said third transistor, to a second input terminal and to a second current source, and the emitters of said third and fourth transistors being coupled together and to a third current source, said output stage being coupled to said collectors of said first and second transistors and being a means for providing a logic compatible output responsive to the differential signal between said first and second resistors.
Claim 2
Dependent Claim 203 words
A sense amplifier for high speed memory applications comprising an input stage having first, second, third and fourth transistors of the same conductivity type, and an output stage, said first and second transistors having their bases coupled together and to a first power supply terminal and having their collectors coupled through first and second resistors, respectively, in said output stage to a second power supply terminal, said collector of said first transistor further being coupled to the collector of said third transistor and said collector of said second transistor being coupled to the collector of said fourth transistor, the emitter of said first transistor being coupled to the base of said fourth transistor, to a first input terminal, and to a first current source, the emitter of said second transistor being coupled to the base of said third transistor, to a second input terminal and to a second current source, and the emitters of said third and fourth transistors being coupled together and to a third current source, said output stage being coupled to said collectors of said first and second transistors and being a means for providing a logic compatible output responsive to the differential signal between said first and second resistors.
Claim 3
Dependent Claim 24 words
The sense amplifier of claim 1 wherein said first, second and third current sources are each resistors coupled to a fifth pOwer supply terminal.
Claim 4
Dependent Claim 29 words
The sense amplifier of claim 1 wherein said first, second and third current sources are each substantially constant current transistor current means coupled to a fifth power supply terminal.
Claim 5
Dependent Claim 56 words
The sense amplifier of claim 1 further comprised of an inhibit means, said inhibit means being coupled to a sixth terminal and being a means for clamping said output in a predetermined logic state in response to an inhibit signal applied thereto, regardless of the condition of the input signals to said third and fourth terminals.
Claim 6
Dependent Claim 68 words
The sense amplifier of claim 4 wherein said inhibit means is a fifth transistor of the same conductivity type as said first, second, third and fourth transistors, the base of said fifth transistor being coupled to said sixth terminal, the collector of said fifth transistor being coupled to said collector of said fourth transistor, and the emitter of said fifth transistor being coupled to said third current source.
Claim 7
Dependent Claim 17 words
The sense amplifier of claim 1 wherein said first, second, third and fourth transistors are NPN transistors.
Claim 8
Dependent Claim 287 words
A sense amplifier comprising first, second, third, fourth, fifth, sixth, seventh, eighth and ninth transistors, all of said transistors being of the same conductivity type, and first, second and third resistors, said first and second transistors having their bases coupled together and to a first terminal and having their collectors coupled through said first and second resistors respectively to a second terminal, said collector of said first transistor further being coupled to the collector of said third transistor and said collector of said second transistor being coupled to the collector of said fourth transistor, the emitter of said first transistor being coupled to the base of said fourth transistor, to a third terminal, and to a first current source, the emitter of said second transistor being coupled to the base of said third transistor, to a fourth terminal and to a second current source, and the emitters of said third and fourth transistors being coupled together and to a third current source, the collectors of said fifth, seventh and eighth transistors being coupled to said second terminal, the collector of said sixth transistor being coupled to said second terminal through said third resistor, the bases of said fifth and eighth transistors being coupled to the collectors of said first and second transistors respectively, the emitters of said fifth and eighth transistors being coupled to fourth and fifth current sources respectively and to the bases of said sixth and seventh transistors respectively, the emitters of said sixth and seventh transistors being coupled together and to a sixth current source, said ninth transistor having its base coupled to the collector of said sixth transistor, its collector coupled to said second terminal, and its emitter coupled to a fifth terminal.
Claim 9
Dependent Claim 287 words
A sense amplifier comprising first, second, third, fourth, fifth, sixth, seventh, eighth and ninth transistors, all of said transistors being of the same conductivity type, and first, second and third resistors, said first and second transistors having their bases coupled together and to a first terminal and having their collectors coupled through said first and second resistors respectively to a second terminal, said collector of said first transistor further being coupled to the collector of said third transistor and said collector of said second transistor being coupled to the collector of said fourth transistor, the emitter of said first transistor being coupled to the base of said fourth transistor, to a third terminal, and to a first current source, the emitter of said second transistor being coupled to the base of said third transistor, to a fourth terminal and to a second current source, and the emitters of said third and fourth transistors being coupled together and to a third current source, the collectors of said fifth, seventh and eighth transistors being coupled to said second terminal, the collector of said sixth transistor being coupled to said second terminal through said third resistor, the bases of said fifth and eighth transistors being coupled to the collectors of said first and second transistors respectively, the emitters of said fifth and eighth transistors being coupled to fourth and fifth current sources respectively and to the bases of said sixth and seventh transistors respectively, the emitters of said sixth and seventh transistors being coupled together and to a sixth current source, said ninth transistor having its base coupled to the collector of said sixth transistor, its collector coupled to said second terminal, and its emitter coupled to a fifth terminal.
Claim 10
Dependent Claim 60 words
The sense amplifier of claim 7 further comprised of an inhibit means, said inhibit means being coupled to a sixth terminal and being a means for clamping the output at said fifth terminal in a predetermined logic state in response to an inhibit signal applied thereto, regardless of the condition of the input signals to said third and fourth terminals.
Claim 11
Dependent Claim 66 words
The sense amplifier of claim 8 wherein said inhibit means is a tenth transistor of the same conductivity type as said first through ninth transistors, the base of said tenth transistor being coupled to said sixth terminal, the collector of said tenth transistor being coupled to said collector of said fourth transistor, and the emitter of said tenth transistor being coupled to said third current source.
Claim 12
Dependent Claim 14 words
The sense amplifier of claim 7 wherein all of said transistors are NPN transistors.

References Cited (Backward Citations)

US3042814A Cited
US3292014A Cited
US3437840A Cited
US3417261A Cited
US3514633A Cited
US3424928A Cited
US3502900A Cited
US3648061A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-09-17 1977-03-19 1977-09-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-09-17 1981-03-19 1981-09-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-09-17 1985-03-19 1985-09-18 $7700.00 Window Closed / Lapsed

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