Patent US5087591A successfully refreshed from Google Patents.
US5087591A
Expired / Lapsed
US
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Contact etch process
Assignee: Texas Instruments Inc
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Filing: 1988-03-16
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Granted: 1992-02-11
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Expires: 2008-03-16
Abstract
Abstract Contact etching is simplified by including a conformal etch stop layer underneath the interlevel or multilevel oxide (MLO). Etching through the unequal thickness of the MLO with sufficient overetching to reliably clear the thickest parts of the MLO layer will therefore not damage the silicon contact areas underneath the thinner parts of the MLO. Process control is also improved. Preferably this conformal etch stop layer is a conductor, and is grounded to configure a field plate over the entire surface of the chip.
Inventors
- 👤 Clarence W. Teng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:47
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
167 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing over a partially fabricated integrated circuit structure a conformal dielectric layer, a conformal intermediate layer over said conformal dielectric layer, and a planarizing layer over said intermediate layer; (b) i. providing a masking layer above said planarizing layer to define contact holes in predetermined locations, ii. selectively etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof. iii. selectively etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose said conformal dielectric layer at said bottoms of said holes, and iv. selectively etching away said exposed portions of said conformal dielectric layer from said bottoms of said holes to expose underlying portions of said partially formed integrated circuit structures; and (c) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 2
Independent Claim
167 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing over a partially fabricated integrated circuit structure a conformal dielectric layer, a conformal intermediate layer over said conformal dielectric layer, and a planarizing layer over said intermediate layer; (b) i. providing a masking layer above said planarizing layer to define contact holes in predetermined locations, ii. selectively etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof. iii. selectively etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose said conformal dielectric layer at said bottoms of said holes, and iv. selectively etching away said exposed portions of said conformal dielectric layer from said bottoms of said holes to expose underlying portions of said partially formed integrated circuit structures; and (c) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 3
Dependent Claim
16 words
The method of claim 1, wherein said conformal dielectric layer is less than 2000 Ångstroms thick.
Claim 4
Dependent Claim
15 words
The method of claim 1, wherein said intermediate layer is less than 3000 Ångstroms thick.
Claim 5
Dependent Claim
19 words
The method of claim 1, wherein said planarizing layer is more than 5000 Ångstroms thick at its thickest point.
Claim 6
Dependent Claim
14 words
The method of claim 1, wherein said intermediate layer consists essentially of a dielectric.
Claim 7
Dependent Claim
13 words
The method of claim 1, wherein said intermediate layer comprises a conductive material.
Claim 8
Dependent Claim
41 words
The method of claim 6, further comprising the additional step, subsequent to said step of etching through exposed portions of said intermediate layer, of depositing sidewall filaments in said contact holes to cover remaining laterally exposed portions of said intermediate layer.
Claim 9
Dependent Claim
33 words
The method of claim 6, further comprising the subsequent step, subsequent to said step of depositing a patterned conductive layer, of making electrical contact between said intermediate layer and a reference voltage source.
Claim 10
Dependent Claim
12 words
The method of claim 6, wherein said intermediate layer comprises doped polysilicon.
Claim 11
Dependent Claim
18 words
The method of claim 1, wherein said step of depositing said planarizing layer comprises spinning on silicate glass.
Claim 12
Dependent Claim
19 words
The method of claim 1, wherein said conformal dielectric layer is deposited by chemical vapor deposition from TEOS gas.
Claim 13
Independent Claim
166 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing a substrate having thereon a partially fabricated integrated circuit structure; (b) providing over said partially fabricated integrated circuit structure a conformal intermediate layer consisting essentially of a material which can be etched selectively with respect to silicon, depositing over said intermediate layer a thick planarizing layer comprising a dielectric material which can be etched selectively with respect to said intermediate layer, and providing a masking layer above said planarizing layer to define contact holes in predetermined locations; (c) etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof, and etching away said exposed portions of said intermediate layer from said bottoms of said contact holes, to expose underlying portions of said partially formed integrated circuit structures: and (d) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 14
Independent Claim
166 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing a substrate having thereon a partially fabricated integrated circuit structure; (b) providing over said partially fabricated integrated circuit structure a conformal intermediate layer consisting essentially of a material which can be etched selectively with respect to silicon, depositing over said intermediate layer a thick planarizing layer comprising a dielectric material which can be etched selectively with respect to said intermediate layer, and providing a masking layer above said planarizing layer to define contact holes in predetermined locations; (c) etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof, and etching away said exposed portions of said intermediate layer from said bottoms of said contact holes, to expose underlying portions of said partially formed integrated circuit structures: and (d) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 15
Independent Claim
125 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing over a partially fabricated integrated circuit structure a conformal intermediate layer, and a planarizing layer over said intermediate layer: (b) providing a masking layer above said planarizing layer to define contact holes in predetermined locations, selectively etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof, and selectively etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose underlying portions of said partially formed integrated circuit structures; and (c) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 16
Independent Claim
125 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing over a partially fabricated integrated circuit structure a conformal intermediate layer, and a planarizing layer over said intermediate layer: (b) providing a masking layer above said planarizing layer to define contact holes in predetermined locations, selectively etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof, and selectively etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose underlying portions of said partially formed integrated circuit structures; and (c) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 17
Independent Claim
162 words
A method for fabricating integrated circuits comprising the steps of: (a) providing over a partially fabricated integrated circuit structure a dielectric layer, an intermediate layer over said dielectric layer and a planarizing layer over said intermediate layer; (b) i. providing a masking layer above said planarizing layer to define contact holes in predetermined locations; ii. selectively etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof; iii. selectively etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose said dielectric layer at said bottoms of said holes; and iv. selectively etching away said exposed portions of said dielectric layer from said bottoms of said holes to expose underlying portions of said partially formed integrated circuit structures; and (c) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 18
Independent Claim
162 words
A method for fabricating integrated circuits comprising the steps of: (a) providing over a partially fabricated integrated circuit structure a dielectric layer, an intermediate layer over said dielectric layer and a planarizing layer over said intermediate layer; (b) i. providing a masking layer above said planarizing layer to define contact holes in predetermined locations; ii. selectively etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof; iii. selectively etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose said dielectric layer at said bottoms of said holes; and iv. selectively etching away said exposed portions of said dielectric layer from said bottoms of said holes to expose underlying portions of said partially formed integrated circuit structures; and (c) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 19
Dependent Claim
15 words
The method of claim 14 wherein said dielectric layer is less than 2000 Angstroms thick.
Claim 20
Dependent Claim
15 words
The method of claim 14 wherein said intermediate layer is less than 3000 Angstroms thick.
Claim 21
Dependent Claim
19 words
The method of claim 14 wherein said planarizing layer is more than 5000 Angstroms thick at its thickest point.
Claim 22
Dependent Claim
14 words
The method of claim 14 wherein said intermediate layer consists essentially of a dielectric.
Claim 23
Dependent Claim
13 words
The method of claim 14 wherein said intermediate layer comprises a conductive material.
Claim 24
Dependent Claim
41 words
The method of claim 19 further comprising the additional step, subsequent to said step of etching through exposed portions of said intermediate layer, of depositing sidewall filaments in said contact holes to cover remaining laterally exposed portions of said intermediate layer.
Claim 25
Dependent Claim
33 words
The method of claim 19 further comprising the subsequent step, subsequent to said step of depositing a patterned conductive layer, of making electrical contact between said intermediate layer and a reference voltage source.
Claim 26
Dependent Claim
12 words
The method of claim 19 wherein said intermediate layer comprises doped polysilicon.
Claim 27
Dependent Claim
18 words
The method of claim 14 wherein said step of depositing said planarizing layer comprises spinning on silicate glass.
Claim 28
Dependent Claim
18 words
The method of claim 14 wherein said dielectric layer is deposited by chemical vapor deposition from TEOS gas.
Claim 29
Independent Claim
165 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing a substrate having thereon a partially fabricated integrated circuit structure; (b) providing over said partially fabricated integrated circuit structure an intermediate layer consisting essentially of a material which can be etched selectively with respect to silicon, depositing over said intermediate layer a thick planarizing layer comprising a dielectric material which can be etched selectively with respect to said intermediate layer, and providing a masking layer above said planarizing layer to define contact holes in predetermined locations; (c) etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof and etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose underlying portions of said partially formed integrated circuit structure; and (d) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 30
Independent Claim
165 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing a substrate having thereon a partially fabricated integrated circuit structure; (b) providing over said partially fabricated integrated circuit structure an intermediate layer consisting essentially of a material which can be etched selectively with respect to silicon, depositing over said intermediate layer a thick planarizing layer comprising a dielectric material which can be etched selectively with respect to said intermediate layer, and providing a masking layer above said planarizing layer to define contact holes in predetermined locations; (c) etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof and etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose underlying portions of said partially formed integrated circuit structure; and (d) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 31
Independent Claim
124 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing over a partially fabricated integrated circuit structure an intermediate layer and a planarizing layer over said intermediate layer; (b) providing a masking layer above said planarizing layer to define contact holes in predetermined locations, selectively etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof and selectively etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose underlying portions of said partially formed integrated circuit structure: and (c) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
Claim 32
Independent Claim
124 words
A method for fabricating integrated circuits, comprising the steps of: (a) providing over a partially fabricated integrated circuit structure an intermediate layer and a planarizing layer over said intermediate layer; (b) providing a masking layer above said planarizing layer to define contact holes in predetermined locations, selectively etching said planarizing layer in accordance with said masking layer to open a plurality of contact holes each having a portion of said intermediate layer exposed at the bottom thereof and selectively etching away said exposed portions of said intermediate layer from said bottoms of said contact holes to expose underlying portions of said partially formed integrated circuit structure: and (c) providing a patterned conductive layer to interconnect said contact holes to configure a predetermined electrical circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-10 | 1995-08-12 | 1996-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-10 | 1999-08-12 | 2000-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-10 | 2003-08-12 | 2004-02-11 | $7700.00 | Window Closed / Lapsed |