Method of making a capacitor with standard self-aligned gate process

Claim 2

In a method of making a semiconductor capacitor device, the steps of: (a) forming a semiconducting region of one conductivity type having a planar surface; (b) forming a layer of dielectric material on said planar surface of said semiconducting region; (c) forming spaced apart first and second openings partially through said layer of dielectric material, said openings being disposed over said semiconducting region; (d) then extending said second opening completely through the remainder of said layer of dielectric material so that a portion of said semiconducting region is exposed; (e) forming an electrically conductive first electrode in said first opening; and (f) forming an electrically conductive second electrode in said second opening in ohmic contact with said portion of said semiconducting region.

Claim 3

The method set forth in claim 1 wherein said first opening has a substantially planar bottom and said first electrode is in contact with a substantial portion of said bottom.

Claim 4

The method set forth in claim 2 wherein said bottom of said first opening is over a major portion of said semiconducting region.

Claim 5

The method set forth in claim 3 wherein: step (b) of forming a layer of dielectric material includes forming individual layers of oxide, nitride, and borophosphosilicate glass; step (c) of forming spaced apart first and second openings through said layer of dielectric material includes forming said first and second openings through said individual layer of borophosphosilicate glass; and step (d) of extending said second opening includes extending said second opening completely through said individual layers of oxide and nitride.

Claim 6

In a method of forming an integrated circuit device the steps of: (a) providing first and second semiconducting regions of one conductivity type each of which has a planar surface; (b) forming a first layer of dielectric material on said planar surfaces of said first and second regions; (c) forming a gate on said first layer of dielectric material directly over said second region; (d) forming a plate region in said first region extending downwardly from said planar surface thereof and forming source and drain regions in said second region extending downwardly from said planar surface thereof on either side of said gate, said plate, source, and drain regions being of another conductivity type having a low resistivity relative to said one conductivity type; (e) forming a second layer of dielectric material on said gate and on said first layer opposite said source, drain, and plate regions; (f) concurrently forming spaced apart first, second, third, and fourth openings through a portion of said second layer of dielectric material, said first and second openings being disposed over said plate region, said third and fourth openings being disposed over said source and drain regions respectively; (g) then extending said second, third, and fourth openings completely through the remainder of said second and first layers of dielectric material so that portions of said plate, drain, and source regions respectively are exposed; (h) forming an electrically conductive first electrode in said first opening; and (i) forming electrically conductive second, third, and fourth electrodes in said second, third, and fourth openings respectively, in ohmic contact with said plate, drain, and source regions respectively.

Claim 7

In a method of forming an integrated circuit device the steps of: (a) providing first and second semiconducting regions of one conductivity type each of which has a planar surface; (b) forming a first layer of dielectric material on said planar surfaces of said first and second regions; (c) forming a gate on said first layer of dielectric material directly over said second region; (d) forming a plate region in said first region extending downwardly from said planar surface thereof and forming source and drain regions in said second region extending downwardly from said planar surface thereof on either side of said gate, said plate, source, and drain regions being of another conductivity type having a low resistivity relative to said one conductivity type; (e) forming a second layer of dielectric material on said gate and on said first layer opposite said source, drain, and plate regions; (f) concurrently forming spaced apart first, second, third, and fourth openings through a portion of said second layer of dielectric material, said first and second openings being disposed over said plate region, said third and fourth openings being disposed over said source and drain regions respectively; (g) then extending said second, third, and fourth openings completely through the remainder of said second and first layers of dielectric material so that portions of said plate, drain, and source regions respectively are exposed; (h) forming an electrically conductive first electrode in said first opening; and (i) forming electrically conductive second, third, and fourth electrodes in said second, third, and fourth openings respectively, in ohmic contact with said plate, drain, and source regions respectively.

Claim 8

The method set forth in claim 5 wherein said first opening has a substantially planar bottom and said first electrode is in contact with a substantial portion of said bottom.

Claim 9

The method set forth in claim 6 wherein said bottom of said first opening is over a major portion of said plate region.

Claim 10

The method set forth in claim 7 wherein step (e) of forming a second layer of dielectric material includes forming individual layers of nitride and borophosphosilicate glass.