US4021789A
Expired / Lapsed
US
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Self-aligned integrated circuits
Assignee: International Business Machines Corp
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Filing: 1975-09-29
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Granted: 1977-05-03
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Expires: 1995-09-29
Abstract
Abstract Semiconductor integrated circuits, including, e.g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semiconductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxide-silicon nitride, the dopant may be ion implanted through the insulating medium to form, e.g., the source and drain electrodes of the transistors as defined by the isolation mediums and the conductive lines. Other elements may be added to the structure to form, e.g., a memory cell. By depositing a conductive medium over the insulated conductive lines, the medium may be appropriately etched to provide desired access lines, capacitor electrodes, ground planes or additional field shields for the cells.
Inventors
- 👤 Anatol Furman
- 👤 Howard Leo Kalter
- 👤 Johann Werner Nagel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:18
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/111; G; G11; G11C; G11C11/00; G11C11/21; G11C11/24; G11C11/34; G11C11/35; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/30; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D84/00; H10D84/80; H10D84/811; H10D84/813
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
179 words
A method for forming an electrical circuit including a field effect transistor in an isolated pocket of a semiconductor material, said transistor having a control electrode and at least one current carrying electrode comprising the steps of: forming a pair of spaced apart isolation strips at the surface of said semiconductor material; extending between said isolation strips substantially orthogonal thereto a plurality of spaced apart conductive lines insulated from the surface of said semiconductor material, said conductive lines being made of a material suitable for defining a barrier to a dopant for said semiconductor material; forming at least one impurity region defined by said isolation strips and said conductive lines in said semiconductor material with said dopant for producing said at least one current carrying electrode of said field effect transistor; applying a signal voltage to a selected one of said lines, said selected line being said control electrode of said field effect transistor; and applying a reference voltage to one of said conductive lines adjacent said selected line to form a field shield for said field effect transistor.
Claim 2
Independent Claim
179 words
A method for forming an electrical circuit including a field effect transistor in an isolated pocket of a semiconductor material, said transistor having a control electrode and at least one current carrying electrode comprising the steps of: forming a pair of spaced apart isolation strips at the surface of said semiconductor material; extending between said isolation strips substantially orthogonal thereto a plurality of spaced apart conductive lines insulated from the surface of said semiconductor material, said conductive lines being made of a material suitable for defining a barrier to a dopant for said semiconductor material; forming at least one impurity region defined by said isolation strips and said conductive lines in said semiconductor material with said dopant for producing said at least one current carrying electrode of said field effect transistor; applying a signal voltage to a selected one of said lines, said selected line being said control electrode of said field effect transistor; and applying a reference voltage to one of said conductive lines adjacent said selected line to form a field shield for said field effect transistor.
Claim 3
Dependent Claim
23 words
A method as set forth in claim 1 wherein said conductive lines are disposed in a direction substantially perpendicular to said isolation strips.
Claim 4
Dependent Claim
41 words
A method as set forth in claim 2 wherein another of said conductive lines adjacent said selected line opposite said one of said conductive lines has a reference voltage applied thereto to form another field shield for said field effect transistor.
Claim 5
Dependent Claim
19 words
A method as set forth in claim 3 wherein said conductive lines are formed on a dual layer insulator.
Claim 6
Dependent Claim
22 words
A method as set forth in claim 4 wherein said dual layer insulator is made of silicon dioxide and silicon nitride layers.
Claim 7
Dependent Claim
33 words
A method as set forth in claim 5 wherein said at least one impurity region is formed by introducing said dopant into said semiconductor material through said silicon nitride layer by ion implantation.
Claim 8
Dependent Claim
17 words
A method as set forth in claim 2 wherein isolation strips are arranged parallel to each other.
Claim 9
Dependent Claim
28 words
A method as set forth in claim 7 wherein said isolation strips are in the form of oxide strips recessed in said semiconductor material at the surface thereof.
Claim 10
Dependent Claim
28 words
A method as set forth in claim 7 wherein said isolation strips are in the form of additional conductive lines insulated from the surface of said semiconductor material.
Claim 11
Dependent Claim
26 words
A method as set forth in claim 9 wherein said conductive lines are made of a material which is self insulatable in an unmasked batch process.
Claim 12
Dependent Claim
18 words
A method as set forth in claim 1 further comprising applying voltages to said current-carrying and control electrodes.
Claim 13
Dependent Claim
38 words
A method as set forth in claim 1 further comprising forming a capacitor on said semiconductor material in an area defined by said pair of isolation strips and said selected line and said one of said conductive lines.
Claim 14
Dependent Claim
28 words
A method as set forth in claim 12 wherein electrodes of said capacitor are formed by said semiconductor material and a conductive material insulated from said semiconductor material.
Claim 15
Dependent Claim
28 words
A method as set forth in claim 13 further comprising applying a bias voltage to said conductive material and a signal to said at least one current-carrying electrode.
Claim 16
Independent Claim
156 words
A method for forming an isolated pocket in a semiconductor material and an electrical circuit therein including a field effect transistor comprising the steps of: forming a first plurality of parallel isolation strips at the surface of said semiconductor material; disposing in a direction substantially perpendicular to said isolation strips a plurality of parallel conductive lines insulated from the surface of said semiconductor material, said conductive lines being characterized as a barrier to a dopant of said semiconductor material; forming impurity regions defined by said isolation strips and said conductive lines in said semiconductor material with said dopant for producing source and drains for said field effect transistor; applying a signal voltage to a selected line of said conductive lines, said selected line being a gate electrode of said field effect transistor; and applying a reference voltage to one of said conductive lines adjacent said selected line to form a shield for said field effect transistor.
Claim 17
Independent Claim
156 words
A method for forming an isolated pocket in a semiconductor material and an electrical circuit therein including a field effect transistor comprising the steps of: forming a first plurality of parallel isolation strips at the surface of said semiconductor material; disposing in a direction substantially perpendicular to said isolation strips a plurality of parallel conductive lines insulated from the surface of said semiconductor material, said conductive lines being characterized as a barrier to a dopant of said semiconductor material; forming impurity regions defined by said isolation strips and said conductive lines in said semiconductor material with said dopant for producing source and drains for said field effect transistor; applying a signal voltage to a selected line of said conductive lines, said selected line being a gate electrode of said field effect transistor; and applying a reference voltage to one of said conductive lines adjacent said selected line to form a shield for said field effect transistor.
Claim 18
Dependent Claim
171 words
A field effect transistor array comprising a semiconductor substrate, a pair of spaced apart isolation strips disposed at the surface of said substrate, a plurality of spaced apart conductive lines extending between said isolation strips and in a substantially orthogonal relationship thereto, an insulating medium disposed between said conductive lines and the surface of said semiconductor substrate, a plurality of current-carrying electrodes disposed in said semiconductor substrate, each of said electrodes being defined by said isolation strips and adjacent pairs of said conductive lines, means for applying a signal voltage to selected lines of said plurality of lines, means for applying a reference voltage to conductive lines adjacent to said selected lines to form field shields, and means for providing an electrical coupling to each of said current carrying electrodes, whereby a plurality of field effect transistors are formed in said array which are electrically isolated from each other within said semiconductor material, each of said transistors including one of said selected lines and current carrying electrodes adjacent said selected lines.
Claim 19
Dependent Claim
171 words
A field effect transistor array comprising a semiconductor substrate, a pair of spaced apart isolation strips disposed at the surface of said substrate, a plurality of spaced apart conductive lines extending between said isolation strips and in a substantially orthogonal relationship thereto, an insulating medium disposed between said conductive lines and the surface of said semiconductor substrate, a plurality of current-carrying electrodes disposed in said semiconductor substrate, each of said electrodes being defined by said isolation strips and adjacent pairs of said conductive lines, means for applying a signal voltage to selected lines of said plurality of lines, means for applying a reference voltage to conductive lines adjacent to said selected lines to form field shields, and means for providing an electrical coupling to each of said current carrying electrodes, whereby a plurality of field effect transistors are formed in said array which are electrically isolated from each other within said semiconductor material, each of said transistors including one of said selected lines and current carrying electrodes adjacent said selected lines.
Claim 20
Dependent Claim
21 words
A field effect transistor array as set forth in claim 16 wherein said isolation strips are strips of recessed silicon dioxide.
Claim 21
Dependent Claim
18 words
A field transistor array as set forth in claim 16 wherein said isolation strips include additional conductive lines.
Claim 22
Dependent Claim
19 words
A field effect transistor array as set forth in claim 18 wherein said conductive lines are made of polysilicon.
Claim 23
Dependent Claim
264 words
A memory array comprising a semiconductor substrate, a plurality of spaced apart isolation strips diposed at the surface of said substrate, a plurality of spaced apart conductive lines arranged substantially perpendicular to said strips, an insulating medium disposed between said conductive lines and the surface of said semiconductor substrate, means for applying a word pulse to a first plurality of selected lines of said plurality of conductive lines, means for applying a reference voltage to a second plurality of selected lines of said plurality of conductive line, one line of said second plurality of selected lines being disposed between adjacent pairs of lines of said first plurality of selected lines, capacitors formed on said semiconductor substrate, each of said capacitors having as a first electrode a portion of the surface of said semiconductor substrate defined by adjacent pairs of isolation strips, one of said first plurality of selected lines and one of said second plurality of selected lines adjacent said one of said first plurality of selected lines, a second electrode of said capacitor being a conductive layer disposed on said insulating medium at said portion of the surface of said semiconductor substrate, means for applying a fixed voltage to said conductive layer of said capacitor, a plurality of current-carrying electrodes, each of said current-carrying electrodes being disposed in said semiconductor substrate at the surface thereof defined by said adjacent pair of isolation strips, said one of said first plurality of selected lines and an adjacent conductive line opposite said capacitor, and means for connecting a bit line to each of said current-carrying electrodes.
Claim 24
Dependent Claim
264 words
A memory array comprising a semiconductor substrate, a plurality of spaced apart isolation strips diposed at the surface of said substrate, a plurality of spaced apart conductive lines arranged substantially perpendicular to said strips, an insulating medium disposed between said conductive lines and the surface of said semiconductor substrate, means for applying a word pulse to a first plurality of selected lines of said plurality of conductive lines, means for applying a reference voltage to a second plurality of selected lines of said plurality of conductive line, one line of said second plurality of selected lines being disposed between adjacent pairs of lines of said first plurality of selected lines, capacitors formed on said semiconductor substrate, each of said capacitors having as a first electrode a portion of the surface of said semiconductor substrate defined by adjacent pairs of isolation strips, one of said first plurality of selected lines and one of said second plurality of selected lines adjacent said one of said first plurality of selected lines, a second electrode of said capacitor being a conductive layer disposed on said insulating medium at said portion of the surface of said semiconductor substrate, means for applying a fixed voltage to said conductive layer of said capacitor, a plurality of current-carrying electrodes, each of said current-carrying electrodes being disposed in said semiconductor substrate at the surface thereof defined by said adjacent pair of isolation strips, said one of said first plurality of selected lines and an adjacent conductive line opposite said capacitor, and means for connecting a bit line to each of said current-carrying electrodes.
Claim 25
Dependent Claim
19 words
A memory array as set forth in claim 20 wherein said insulation strips are strips of recessed silicon dioxide.
Claim 26
Dependent Claim
17 words
A memory array as set forth in claim 20 wherein said insulation strips include additional conductive lines.
Claim 27
Dependent Claim
17 words
A memory array as set forth in claim 20 wherein said conductive lines are made of polysilicon.
Claim 28
Dependent Claim
27 words
A memory array as set forth in claim 23 wherein said insulating medium is a dual layer insulator, one of said layers being made of silicon nitride.
Claim 29
Dependent Claim
50 words
A memory array as set forth in claim 20 wherein each of said current-carrying electrodes is disposed between an adjacent pair of said first plurality of selected lines and the conductive layer of said capacitors disposed on opposite sides of one of said second plurality of selected lines are interconnected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-02 | 1980-11-01 | 1981-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-02 | 1984-11-01 | 1985-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-02 | 1988-11-01 | 1989-05-03 | $7700.00 | Window Closed / Lapsed |