US3893152A
Expired / Lapsed
US
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Metal nitride oxide semiconductor integrated circuit structure
Assignee: Individual
•
Filing: 1973-07-25
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Granted: 1975-07-01
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Expires: 1993-07-25
Abstract
Abstract Method and apparatus for providing a metal nitride oxide semiconductor (MNOS) memory in the form of a matrix array of either capacitors and/or transistors having polarizing potentials applied thereto for representing one of two binary logic states. Structurally, the array is comprised of a thin epitaxial layer of one type, for example n-type semiconductivity grown on a substrate of opposite or p-type semiconductivity. Parallel rows of silicon dioxide are infused into the epitaxial layer to provide strip regions of isolation between separated regions of first conductivity also forming substantially parallel rows. Transversely to the parallel sublayer rows of n-type semiconductivity and silicon dioxide isolation are a plurality of parallel columns of common gates, either metal or silicon. The columns of gates are separated from the parallel rows of n-type semiconductivity by intermediate contiguous layers of silicon dioxide and silicon nitride. Such a configuration describes a matrix array of capacitors; however, a matrix of transistors is formed by additionally diffusing a dopant of for example p+type semiconductivity into the regions of n-type semiconductivity on either side of the parallel columns of common gates.
Inventors
- 👤 Hung Chang Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:08
CPC Classifications
H; H10; H10B; H10B41/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H10B69/00; Y; Y10; Y10S; Y10S148/00; Y10S148/085
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
184 words
AN ARRAY OF MNOS DEVICES HAVING BINARY LOGIC OPERATING STATES THEREBY BEING ADAPTED TO OPERATE AS A MATRIX OF DISCRETE STORAGE CELLS, THE IMPROVEMENT COMPRISING: A BODY OF FIRST TYPE SEMICONDUCTOR MATERIAL, A CONTINUOUS PLANAR EPITAXIAL LAYER OF SUBSTANTIALLY UNIFORM THICKNESS FORMED ON THE SURFACE OF SAID BODY CONSISTING OF A PLURALITY OF ACTIVE REGIONS COMPRISING ALTERNATE ROWS OF SECOND TYPE SEMICONDUCTIVE MATERIAL, SEPARATED BY CONTIGUOUS INACTIVE REGIONS COMPRISING INTERVENING ROWS OF DIELECTRIC ISOLATION MATERIAL, SAID ROWS EXTENDING THROUGH THE ENTIRE THICKNESS OF THE EPITAXIAL LAYER, A PLURALITY OF SEPARATED COLUMNS OF MNOS GATES EXTENDING SUBSTANTIALLY TRANSVERSELY ACROSS SAID ROWS OF SECOND TYPE SEMICONDUCTIVE MATERIAL AND SAID ROWS OF DIELECTRIC ISOLATION MATERIAL, SAID COLUMNS EACH COMPRISING GATE MATERIAL SEPARATED FROM SAID ROWS BY RESPECTIVE COLUMNS OF SUBSTANTIALLY THE SAME WIDTH DIMENSION AS SAID GATE MATERIAL OF A FIRST LAYER OF DIELECTRIC MATERIAL CONTIGUOUS WITH SAID ROWS AND A SECOND LAYER OF DIELECTRIC MATERIAL CONTIGUOUSLY SANDWICHED BETWEEN SAID FIRST LAYER OF DIELECTRIC MATERIAL AND SAID GATE MATERIAL, EACH GATE PORTION AND THE ACTIVE REGION SUBTENDED THEREBY COMPRISING A SEPARATE STORAGE CELL HAVING A CAPACITIVE NODE.
Claim 2
Dependent Claim
184 words
AN ARRAY OF MNOS DEVICES HAVING BINARY LOGIC OPERATING STATES THEREBY BEING ADAPTED TO OPERATE AS A MATRIX OF DISCRETE STORAGE CELLS, THE IMPROVEMENT COMPRISING: A BODY OF FIRST TYPE SEMICONDUCTOR MATERIAL, A CONTINUOUS PLANAR EPITAXIAL LAYER OF SUBSTANTIALLY UNIFORM THICKNESS FORMED ON THE SURFACE OF SAID BODY CONSISTING OF A PLURALITY OF ACTIVE REGIONS COMPRISING ALTERNATE ROWS OF SECOND TYPE SEMICONDUCTIVE MATERIAL, SEPARATED BY CONTIGUOUS INACTIVE REGIONS COMPRISING INTERVENING ROWS OF DIELECTRIC ISOLATION MATERIAL, SAID ROWS EXTENDING THROUGH THE ENTIRE THICKNESS OF THE EPITAXIAL LAYER, A PLURALITY OF SEPARATED COLUMNS OF MNOS GATES EXTENDING SUBSTANTIALLY TRANSVERSELY ACROSS SAID ROWS OF SECOND TYPE SEMICONDUCTIVE MATERIAL AND SAID ROWS OF DIELECTRIC ISOLATION MATERIAL, SAID COLUMNS EACH COMPRISING GATE MATERIAL SEPARATED FROM SAID ROWS BY RESPECTIVE COLUMNS OF SUBSTANTIALLY THE SAME WIDTH DIMENSION AS SAID GATE MATERIAL OF A FIRST LAYER OF DIELECTRIC MATERIAL CONTIGUOUS WITH SAID ROWS AND A SECOND LAYER OF DIELECTRIC MATERIAL CONTIGUOUSLY SANDWICHED BETWEEN SAID FIRST LAYER OF DIELECTRIC MATERIAL AND SAID GATE MATERIAL, EACH GATE PORTION AND THE ACTIVE REGION SUBTENDED THEREBY COMPRISING A SEPARATE STORAGE CELL HAVING A CAPACITIVE NODE.
Claim 3
Dependent Claim
49 words
The array of MNOS devices as defined by claim 1 and additionally including regions of first type semiconductivity diffused in said active regions adjacent and between said columns of MNOS gates defining drain and source regions of series connected transistors in each row of second type of semiconductor material.
Claim 4
Dependent Claim
72 words
The array of MNOS devices as defined by claim 1 wherein said body of first type semiconductive material is comprises of a substrate of p-type semiconductive material, said plurality of rows of second type semiconductive material is comprised of n-type semiconductive material, said isolation regions of dielectric material and said first layer of dIelectric material is comprised of silicon dioxide, and said second layer of dielectric material is comprised of silicon nitride.
Claim 5
Dependent Claim
34 words
The array of MNOS devices as defined by claim 3 and additionally including diffused regions of p type semiconductivity in said rows of n-type semiconductivity material adjacent and between said columns of MNOS gates.
Claim 6
Dependent Claim
42 words
The array of MNOS devices as defined by claim 1 wherein said gate material is comprised of conductive metal, said first layer of dielectric material is comprised of silicon dioxide, and said second layer of dielectric material is comprised of silicon nitride.
Claim 7
Dependent Claim
36 words
The array of MNOS devices as defined by claim 5 and additionally including diffused regions of first type semiconductivity diffused in said rows of second type semiconductive material adjacent and between said columns of MNOS gates.
Claim 8
Dependent Claim
41 words
The array of MNOS devices as defined by claim 1 wherein said gate material is comprised of silicon, said first layer of dielectric material is comprised of silicon dioxide, and said second layer of dielectric material is comprised of silicon nitride.
Claim 9
Dependent Claim
46 words
The array as defined by claim 7 and additionally including regions of first type semiconductivity diffused in said rows of second type semiconductive material between and adjacent said columns of silicon gate material, said first layer of silicon dioxide and said second layer of silicon nitride.
Claim 10
Dependent Claim
60 words
The array of MNOS devices as defined by claim 1 wherein said plurality of rows of semiconductive material and dielectric isolation material are comprised of substantially parallel alternating rows and said plurality of columns of gate material together with the respective columns of first and second layers of dielectric material are comprised of substantially parallel columns of substantially constant separation.
Claim 11
Dependent Claim
58 words
The array of MNOS devices as defined by claim 1 wherein said isolation regions of dielectric material are comprised of regions of silicon dioxide contiguous with the respective adjacent rows of second type semiconductor material, said uniform thickness providing a planar outer surface over which are formed said transverse columns of MNOS gates in substantially equally spaced relationship.
References Cited (Backward Citations)
GB1160744A
Cited
US3691535A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-30 | 1978-12-30 | 1979-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-30 | 1982-12-30 | 1983-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-30 | 1986-12-30 | 1987-07-01 | $7700.00 | Window Closed / Lapsed |