Process for obtaining high-voltage N channel transistors particularly for EEPROM memories with CMOS technology

Claim 1

Process for obtaining a high-voltage N-channel transistor, particularly for an EEPROM memory with CMOS technology, comprising in succession the steps of: a) N - doping at least a first portion of a P-type semiconductor substrate surface which has been covered with an oxide layer, b) oxidizing the doped first portion of the substrate surface to form a gate oxide layer which is thicker than gate oxide layer thicknesses on any other portion of the substrate surface as a result of the N - doping, c) deposite and definition of an N + doped polysilicon layer on a part of said doped first portion and on an adjacent portion of the substrate surface to form a gate strip, d) oxidizing the gate strip, e) N + doping the remaining part of said doped first portion of the substrate surface which does not have the N + doped polysilicon layer deposited and defined thereon, and simultaneously N + doping another portion of the substrate surface at a side of the gate strip opposite to that of said doped first portion to form drain and source areas.