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US5081514A Expired / Lapsed US ⏱️ 0.0 years remaining

Protection circuit associated with input terminal of semiconductor device

Assignee: NEC Corp
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Filing: 1989-12-27
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Granted: 1992-01-14
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Expires: 2009-12-27
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Abstract

Abstract A semiconductor device fabricated on an n-type substrate has a plurality of signal input terminals each associated with a protection circuit for preventing an internal integrated circuit from being damaged by an undesirable surge voltage. The protection circuit is formed in a p-type well and comprises an n-type impurity region supplied with the surge voltage, an inner well contact area located inside of the n-type impurity region and an outer well contact area located outside of the n-type impurity region, so that a large amount of current flows from both side surfaces of the n-type impurity region into the inner and outer well contact areas, thereby decreasing the voltage level in the p-type well for preventing the p-n junction between the well and the substrate from destruction.

Inventors

  • 👤 Junji Ueoka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 02:59
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/611

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 403 words
A protection circuit associated with a terminal for protecting an internal circuit integrated on a semiconductor substrate of a first conductivity type from being damaged by an excess terminal voltage, said semiconductor substrate being covered with an insulating film, said terminal extending across said insulating film, comprising: a) a well of a second conductivity type formed in said semiconductor substrate, said second conductivity type being opposite to said first conductivity type; b) a first impurity region of said first conductivity type formed in said well and located between inner and outer regions of said well, said inner region being located inside of said first impurity region, said outer region being located outside of said first impurity region, said terminal having a trunk portion and first and second branch portions extending from said trunk portion and located over said first impurity region, said first and second branch portions having respective distal ends spaced apart from each other by a distance, said branch portions of said terminal being in contact with said first impurity region through a first contact window formed in said insulating film; c) a second impurity region heavily doped with impurity atoms of said second conductivity type and formed in said inner region of said well; d) a third impurity region heavily doped with impurity atoms of said second conductivity type and formed in said outer region of said well; and e) a current discharge line extending across said insulating film having a trunk portion in contact with said third impurity region through a second contact window formed in said insulating film, and third and fourth branch portions being in contact with said third impurity region through said second contact window and extending so that said third and fourth branch portions substantially surround said terminal, said third and fourth branch portions having respective distal ends facing both sides of said trunk portion, respectively, said current discharge line further having a fifth branch portion extending through said terminal gap and being in contact with said second impurity region through a third contact window formed in said insulating film, a p-n junction being formed between said first impurity region and said well, said p-n junction being broken down upon application of said excess terminal voltage so that current flows from said terminal through said first impurity region, said p-n junction, said well and said second and third impurity regions to said current discharge line.
Claim 2
Dependent Claim 403 words
A protection circuit associated with a terminal for protecting an internal circuit integrated on a semiconductor substrate of a first conductivity type from being damaged by an excess terminal voltage, said semiconductor substrate being covered with an insulating film, said terminal extending across said insulating film, comprising: a) a well of a second conductivity type formed in said semiconductor substrate, said second conductivity type being opposite to said first conductivity type; b) a first impurity region of said first conductivity type formed in said well and located between inner and outer regions of said well, said inner region being located inside of said first impurity region, said outer region being located outside of said first impurity region, said terminal having a trunk portion and first and second branch portions extending from said trunk portion and located over said first impurity region, said first and second branch portions having respective distal ends spaced apart from each other by a distance, said branch portions of said terminal being in contact with said first impurity region through a first contact window formed in said insulating film; c) a second impurity region heavily doped with impurity atoms of said second conductivity type and formed in said inner region of said well; d) a third impurity region heavily doped with impurity atoms of said second conductivity type and formed in said outer region of said well; and e) a current discharge line extending across said insulating film having a trunk portion in contact with said third impurity region through a second contact window formed in said insulating film, and third and fourth branch portions being in contact with said third impurity region through said second contact window and extending so that said third and fourth branch portions substantially surround said terminal, said third and fourth branch portions having respective distal ends facing both sides of said trunk portion, respectively, said current discharge line further having a fifth branch portion extending through said terminal gap and being in contact with said second impurity region through a third contact window formed in said insulating film, a p-n junction being formed between said first impurity region and said well, said p-n junction being broken down upon application of said excess terminal voltage so that current flows from said terminal through said first impurity region, said p-n junction, said well and said second and third impurity regions to said current discharge line.
Claim 3
Dependent Claim 21 words
A protection circuit as set forth in claim 1, in which said second impurity region has a generally rectangular outer periphery.
Claim 4
Dependent Claim 22 words
A protection circuit as set forth in claim 2, in which said first impurity region has generally rectangular outer and inner peripheries.
Claim 5
Dependent Claim 20 words
A protection circuit as set forth in claim 3, in which said third impurity region has generally rectangular inner periphery.
Claim 6
Dependent Claim 21 words
A protection circuit as set forth in claim 1, in which said second impurity region has a generally polygonal outer periphery.
Claim 7
Dependent Claim 22 words
A protection circuit as set forth in claim 5, in which said first impurity region has generally polygonal outer and inner peripheries.
Claim 8
Dependent Claim 21 words
A protection circuit as set forth in claim 6, in which said third impurity region has a generally polygonal inner periphery.
Claim 9
Dependent Claim 17 words
A protection circuit as set forth in claim 7, in which said generally polygonal peripheries are octagonal.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-01-13 1995-07-15 1996-01-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-01-13 1999-07-15 2000-01-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-01-13 2003-07-15 2004-01-14 $7700.00 Window Closed / Lapsed

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