US4189739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor overload protection structure
Assignee: AT&T Inc
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Filing: 1978-03-08
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Granted: 1980-02-19
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Expires: 1998-03-08
Abstract
Abstract An input voltage overload protection semiconductor structure useful with MOS circuitry consists of a p-region in an n-substrate with p+ type regions formed on both sides of the p-region and an n+ type region centrally located in the p-region. Input signals are applied to the first p+ region. The gate of an MOS structure to be protected from voltage overload is connected to the second p+ type region. A power supply used with the MOS structure is connected to the n+ region. This structure provides significantly greater load protection than the standard resistor-diode-resistor circuit.
Inventors
- 👤 John A. Copeland, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:21
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/611
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
156 words
A semiconductor structure comprising: a semiconductor body having a major surface and including a bulk portion of a first conductivity type; a first region located within the semiconductor body and extending to the major surface and being of a second conductivity type; a second region located within the first region and extending to the major surface and being of the first conductivity type; and third and fourth regions within the body each contiguous with at least portions of the first region and extending to the major surface and being of the second conductivity type; the third and fourth regions being of higher impurity concentration than the second region and being separated from each other and from the second region; the third region having an electrode coupled thereto which serves as an input port; the fourth region having an electrode coupled thereto which serves as an output port; and the second region having an electrode coupled thereto.
Claim 2
Dependent Claim
156 words
A semiconductor structure comprising: a semiconductor body having a major surface and including a bulk portion of a first conductivity type; a first region located within the semiconductor body and extending to the major surface and being of a second conductivity type; a second region located within the first region and extending to the major surface and being of the first conductivity type; and third and fourth regions within the body each contiguous with at least portions of the first region and extending to the major surface and being of the second conductivity type; the third and fourth regions being of higher impurity concentration than the second region and being separated from each other and from the second region; the third region having an electrode coupled thereto which serves as an input port; the fourth region having an electrode coupled thereto which serves as an output port; and the second region having an electrode coupled thereto.
Claim 3
Dependent Claim
28 words
The apparatus of claim 1 wherein the semiconductor body and second region are both of n-type conductivity and the first, third, and fourth regions are of p-type conductivity.
Claim 4
Dependent Claim
169 words
A structure for inclusion in a semiconductor body having a circuit which is to be protected and having a major surface and a bulk portion of a first conductivity type comprising: a first region located within a portion of the semiconductor body and extending to the major surface and being of a second conductivity type; a second region located within a portion of the first region and extending to the major surface and being of the first conductivity type; third and fourth regions contiguous with at least portions of the first region and extending to the major surface and being of the second conductivity type; the third and fourth regions being of higher impurity concentration than the second region and being separated from each other and from the second region; and the second, third and fourth regions each having a separate electrode coupled thereto; the electrode coupled to the third region serving as an input port; and the electrode coupled to the fourth region being coupled to the circuit.
Claim 5
Dependent Claim
169 words
A structure for inclusion in a semiconductor body having a circuit which is to be protected and having a major surface and a bulk portion of a first conductivity type comprising: a first region located within a portion of the semiconductor body and extending to the major surface and being of a second conductivity type; a second region located within a portion of the first region and extending to the major surface and being of the first conductivity type; third and fourth regions contiguous with at least portions of the first region and extending to the major surface and being of the second conductivity type; the third and fourth regions being of higher impurity concentration than the second region and being separated from each other and from the second region; and the second, third and fourth regions each having a separate electrode coupled thereto; the electrode coupled to the third region serving as an input port; and the electrode coupled to the fourth region being coupled to the circuit.
Claim 6
Dependent Claim
163 words
Monolithic semiconductor apparatus comprising a protective portion and a functional portion including at least one MOS structure in which the protective portion comprises: a bulk portion of one conductivity type; a first region of the opposite conductivity type within the bulk portion and extending in part to a connecting surface; a second region of the one conductivity type within the first region and extending in part to the connecting surface; separate third and fourth regions of the opposite conductivity type and of higher conductivity than the first region and spaced apart on opposite sides of the second region, each being contiguous with at least part of said first region and extending in part to the connecting surface; electrode means coupled to the third region for receiving input signals; electrode means coupled to the second region for receiving operating potentials; and means for providing a low resistance path between the fourth region and an input terminal of the MOS structure of the functional portion.
Claim 7
Dependent Claim
163 words
Monolithic semiconductor apparatus comprising a protective portion and a functional portion including at least one MOS structure in which the protective portion comprises: a bulk portion of one conductivity type; a first region of the opposite conductivity type within the bulk portion and extending in part to a connecting surface; a second region of the one conductivity type within the first region and extending in part to the connecting surface; separate third and fourth regions of the opposite conductivity type and of higher conductivity than the first region and spaced apart on opposite sides of the second region, each being contiguous with at least part of said first region and extending in part to the connecting surface; electrode means coupled to the third region for receiving input signals; electrode means coupled to the second region for receiving operating potentials; and means for providing a low resistance path between the fourth region and an input terminal of the MOS structure of the functional portion.
References Cited (Backward Citations)
US3967295A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-18 | 1983-08-20 | 1984-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-18 | 1987-08-20 | 1988-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-18 | 1991-08-20 | 1992-02-19 | $7700.00 | Window Closed / Lapsed |