Method for operating a multiple page programmable logic device

Claim 1

A method for operating a logic array circuit comprising: a plurality of L input leads for receiving a plurality of input signals, where L is a first positive integer; a set of N first logic arrays, where N is a second positive integer greater than or equal to one, each of said N first logic arrays including means for receiving signals related to selected ones of said input signals, a plurality of P intermediate output signal leads, a plurality of logic gates for providing P intermediate output signals on said P intermediate signal leads as a function of said signals related to selected ones of said input signals, where P is a third positive integer associated with that one of said N first logic arrays; and a set of M second logic arrays, where M is a fifth positive integer greater than or equal to one, each of said second logic arrays including one or more input leads for receiving input signals related to said intermediate output signals of said selected ones of said first logic arrays, a plurality of S output leads, where S is a positive integer, one or more logic gates for providing output signals on said S output leads as a function of said input signals of said second logic array, said method comprising the steps of: selecting a subset of D of said first logic arrays, where D is a fourth positive integer greater than or equal to one; and selecting a subset of G of said M second logic arrays for receiving said input signals to related said intermediate output signals of said set of D of said first logic arrays and providing a set of output signals, where G is a sixth positive integer; wherein at least one of said steps of selecting performs in response to one or more of said input signals.

Claim 2

A method for operating a logic array circuit comprising: a plurality of L input leads for receiving a plurality of input signals, where L is a first positive integer; a set of N first logic arrays, where N is a second positive integer greater than or equal to one, each of said N first logic arrays including means for receiving signals related to selected ones of said input signals, a plurality of P intermediate output signal leads, a plurality of logic gates for providing P intermediate output signals on said P intermediate signal leads as a function of said signals related to selected ones of said input signals, where P is a third positive integer associated with that one of said N first logic arrays; and a set of M second logic arrays, where M is a fifth positive integer greater than or equal to one, each of said second logic arrays including one or more input leads for receiving input signals related to said intermediate output signals of said selected ones of said first logic arrays, a plurality of S output leads, where S is a positive integer, one or more logic gates for providing output signals on said S output leads as a function of said input signals of said second logic array, said method comprising the steps of: selecting a subset of D of said first logic arrays, where D is a fourth positive integer greater than or equal to one; and selecting a subset of G of said M second logic arrays for receiving said input signals to related said intermediate output signals of said set of D of said first logic arrays and providing a set of output signals, where G is a sixth positive integer; wherein at least one of said steps of selecting performs in response to one or more of said input signals.

Claim 33

A method for operating a logic array circuit comprising: a plurality of L input leads for receiving a plurality of input signals, where L is a first positive integer; and a set of N first logic arrays, where N is a second positive integer greater than or equal to one, each of said N first logic arrays including means for receiving signals related to selected ones of said input signals, a plurality of P output signal leads, a plurality of logic gates for providing P output signals on said P signal leads as a function of said signals related to selected ones of said input signals, where P is a third positive integer associated with that one of said N first logic arrays, said method comprising the steps of: storing a first plurality of pages of information defining desired logic configuration patterns; and downloading said information from a selected one or more of said first plurality of pages to said set of N logic arrays, thereby configuring said set of N first logic arrays to perform one or more logical functions.

Claim 34

A method for operating a logic array circuit comprising: a plurality of L input leads for receiving a plurality of input signals, where L is a first positive integer; and a set of N first logic arrays, where N is a second positive integer greater than or equal to one, each of said N first logic arrays including means for receiving signals related to selected ones of said input signals, a plurality of P output signal leads, a plurality of logic gates for providing P output signals on said P signal leads as a function of said signals related to selected ones of said input signals, where P is a third positive integer associated with that one of said N first logic arrays, said method comprising the steps of: storing a first plurality of pages of information defining desired logic configuration patterns; and downloading said information from a selected one or more of said first plurality of pages to said set of N logic arrays, thereby configuring said set of N first logic arrays to perform one or more logical functions.