PLA With time division multiplex feature for improved density

Claim 1

In a PLA of the type having an array having input lines, output lines, and internal lines crossing over the input and output lines, and interconnection elements in a predetermined pattern at crossover points of the array, means for supplying logic signals to be operated on by the array, and input circuits connected to receive a binary number of said logic signals and connected to a binary number of said input lines of the array for supplying partitioning functions of said logic signals to the connected input lines, where a binary number is a non-negative integral power of 2, and output circuits for receiving logic signals from the output lines of the array, wherein the improvement comprises, means for producing timing signals defining a plurality of timing phases, means connecting each of said timing signals to a disjunct plurality of said input circuits, whereby each timing phase corresponds to a set of input lines of the array, and means in each input circuit responsive to its timing signal to enable the input circuit to supply said partitioning function and responsive to the complement of its timing signal to inhibit the input circuit, and means connecting said timing signals to said output circuits and means in each output circuit responsive to its phase of the timing signals to enable the associated output circuit to receive and store a signal on the associated output line and responsive to the complement of said corresponding phase to inhibit the output circuit, whereby the internal lines of the PLA are shared by a plurality of sets of input lines, each set having a selected logic function that is enabled at a separate time phase in the operation of the array.