Fabrication process for programmable and erasable MOS memory device

Claim 2

A process of fabricating a programmable and erasable EEPROM memory device comprising, defining an active memory area for an EEPROM device on a semiconductor wafer and forming a layer of filed oxide in nonactive areas of said wafer, then forming a thin oxide layer over the entire active memory area, said thin oxide layer having a thickness in a range from 70Å to 150Å, then depositing a first polysilicon layer on said wafer and selectively removing said first polysilicon layer so as to define a floating gate in said active memory area of the EEPROM device, then selectively implanting an N-type impurity after the definition of said floating gate into said active memory area of said wafer adjacent to one edge of said floating gate, to form a drain portion in the active area, the drain portion being a tunneling region of the EEPROM device using the edge of the floating gate to locate the drain portion adjacent to the floating gate, forming a second oxide layer on said wafer including over said polysilicon floating gate, depositing a second polysilicon layer over said second oxide layer, selectively removing said second polysilicon layer and said second oxide layer to define control gates, said control gates including a sense gate located over said floating gate, forming source and drain active areas in said active memory area, the drain joined to the previously formed drain portion, forming source and drain active areas in said active memory area, the drain joined to the previously formed drain portion, forming a covering of insulative material over said wafer, said covering having via holes therein to selected sources, drains and gates, and forming a layer of conductive lines over said covering connected to said selected sources, drains and gates through said via holes, and subsequent to implanting said N-type impurity, heating said wafer, driving a portion of said N-type impurity comprising the drain portion under a portion of said floating gate, without driving the subsequently formed source and drain active areas under the floating gate, for programming and erasing the MOS memory device by tunneling.

Claim 3

The process of claim 1 wherein said N-type impurity is selected from the group consisting of phosphorus and arsenic.

Claim 4

The process of claim 1 wherein said N-type impurity is implanted with an implantation energy of from 50 keV to 100 keV to a dose in a range from 0.5×10 14 /cm 2 to 5.0×10 14 /cm 2 .

Claim 5

A process of fabricating a programmable and erasable floating gate EEPROM device and an electrically connected select transistor comprising, defining active areas on a semiconductor wafer for an EEPROM device and an adjacent select transistor, the two devices sharing a single active area for mutual electrical connection, and forming a layer of field oxide in nonactive areas of said wafer, then forming a thin oxide layer over the entire active area of the EEPROM device, said thin oxide layer having a thickness in a range from 70Å to 150Å, and a thicker oxide elsewhere including the active area of the select transistor, then depositing a first polysilicon layer on said wafer and selectively removing said first polysilicon layer so as to define a floating gate in said active memory area of the EEPROM device, selectively implanting an N-type impurity after the definition of said floating gate into said active areas of said wafer to form a drain portion for each EEPROM device, the drain portion being a tunneling region adjacent to one edge of said floating gate, using the edge of the floating gate to locate the drain portion adjacent to the floating gate, forming a second oxide layer on said wafer including over said polysilicon floating gate, depositing a second polysilicon layer over said second oxide layer, selectively removing said second polysilicon layer and said second oxide layer to define control gates for both the EEPROM device and the select transistor, said control gates including a sense gate located over said floating gate for the EEPROM device, forming source and drain active areas in said active memory area, the drain joined to the previously formed drain portion, forming a covering of insulative material over said wafer, said covering having via holes therein to selected sources, drains and gates, and forming a layer of conductive lines over said covering connected to said selected sources, drains and gates through said via holes, and subsequent to implanting said N-type impurity, heating said wafer driving a portion of said N-type drain impurity of the EEPROM device comprising the drain portion under a portion of said floating gate, without driving the subsequently formed source and drain active areas under the floating gate, for programming and erasing the EEPROM device by tunneling.

Claim 6

A process of fabricating a programmable and erasable floating gate EEPROM device and an electrically connected select transistor comprising, defining active areas on a semiconductor wafer for an EEPROM device and an adjacent select transistor, the two devices sharing a single active area for mutual electrical connection, and forming a layer of field oxide in nonactive areas of said wafer, then forming a thin oxide layer over the entire active area of the EEPROM device, said thin oxide layer having a thickness in a range from 70Å to 150Å, and a thicker oxide elsewhere including the active area of the select transistor, then depositing a first polysilicon layer on said wafer and selectively removing said first polysilicon layer so as to define a floating gate in said active memory area of the EEPROM device, selectively implanting an N-type impurity after the definition of said floating gate into said active areas of said wafer to form a drain portion for each EEPROM device, the drain portion being a tunneling region adjacent to one edge of said floating gate, using the edge of the floating gate to locate the drain portion adjacent to the floating gate, forming a second oxide layer on said wafer including over said polysilicon floating gate, depositing a second polysilicon layer over said second oxide layer, selectively removing said second polysilicon layer and said second oxide layer to define control gates for both the EEPROM device and the select transistor, said control gates including a sense gate located over said floating gate for the EEPROM device, forming source and drain active areas in said active memory area, the drain joined to the previously formed drain portion, forming a covering of insulative material over said wafer, said covering having via holes therein to selected sources, drains and gates, and forming a layer of conductive lines over said covering connected to said selected sources, drains and gates through said via holes, and subsequent to implanting said N-type impurity, heating said wafer driving a portion of said N-type drain impurity of the EEPROM device comprising the drain portion under a portion of said floating gate, without driving the subsequently formed source and drain active areas under the floating gate, for programming and erasing the EEPROM device by tunneling.