US5073727A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cmos inverter with noise reduction feedback means
Assignee: Fujitsu VLSI Ltd
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Filing: 1989-05-25
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Granted: 1991-12-17
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Expires: 2009-05-25
Abstract
Abstract A semiconductor integrated circuit having a complementary metal oxide semiconductor (CMOS) inverter includes a CMOS inverter circuit and a noise reduction circuit. The CMOS inverter has input and output terminals, and inverts an input signal applied to the input terminal to thereby output an output signal through the output terminal. The noise reduction circuit, which is connected to the CMOS inverter, rapidly passes a current supplied from the CMOS inverter to the low-potential power source until a potential of the output terminal decreases to a predetermined potential in response to an increase in potential of the input signal, and slowly passes the current after the potential of the output terminal reaches the predetermined potential.
Inventors
- 👤 Harumi Shizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
146 words
A semiconductor integrated circuit comprising: a first MOS transistor coupled between a first power supply line and an output node of the semiconductor integrated circuit, said first MOS transistor having a first channel type; a second MOS transistor coupled between the output node and a first intermediate node, said second MOS transistor having a second channel type; a third MOS transistor coupled between the first intermediate node and a second power supply line, said third MOS transistor having the second channel type; and a fourth MOS transistor coupled between the first intermediate node and the second power supply line, said fourth MOS transistor having the second channel type, wherein gate electrodes of said first, second and third MOS transistors being commonly coupled to an input node of the semiconductor integrated circuit, and a gate electrode of said fourth MOS transistor being coupled to the output node.
Claim 2
Dependent Claim
146 words
A semiconductor integrated circuit comprising: a first MOS transistor coupled between a first power supply line and an output node of the semiconductor integrated circuit, said first MOS transistor having a first channel type; a second MOS transistor coupled between the output node and a first intermediate node, said second MOS transistor having a second channel type; a third MOS transistor coupled between the first intermediate node and a second power supply line, said third MOS transistor having the second channel type; and a fourth MOS transistor coupled between the first intermediate node and the second power supply line, said fourth MOS transistor having the second channel type, wherein gate electrodes of said first, second and third MOS transistors being commonly coupled to an input node of the semiconductor integrated circuit, and a gate electrode of said fourth MOS transistor being coupled to the output node.
Claim 3
Dependent Claim
52 words
A semiconductor integrated circuit as claimed in claim 1, further comprising a fifth MOS transistor coupled between said third MOS transistor and the second power supply line, and a gate of said fifth MOS transistor being coupled to the input node, and further said fifth MOS transistor having the second channel type.
Claim 4
Dependent Claim
59 words
A semiconductor integrated circuit as claimed in claim 1, further comprising: a fifth MOS transistor coupled between the first intermediate node and the second power supply line, a gate electrode of said fifth MOS transistor and the gate of said fourth MOS transistor being coupled to the output node, and said fifth MOS transistor having the second channel type.
Claim 5
Dependent Claim
26 words
A semiconductor integrated circuit as claimed in claim 1, wherein said second MOS transistor has a mutual transconductance higher than that of said first MOS transistor.
Claim 6
Dependent Claim
26 words
A semiconductor integrated circuit as claimed in claim 1, wherein said second MOS transistor has a mutual transconductance higher than that of said first MOS transistor.
Claim 7
Dependent Claim
17 words
A semiconductor integrated circuit device as claimed in claim 1, wherein said circuit forms an output buffer.
Claim 8
Dependent Claim
223 words
A semiconductor integrated circuit having a complementary metal oxide semiconductor (CMOS) inverter device, comprising: a CMOS inverter including a first P-channel MOS transistor having a drain, source and gate, and a first N-channel MOS transistor having a drain, source and gate, the source of said first P-channel MOS transistor being connected to a high-potential power source the drains of said first P- and N-channel MOS transistors being connected together and forming an output of said circuit, and the gates of said first P-channel and N-channel MOS transistors being mutually connected and supplied with an input signal; a second N-channel MOS transistor having a drain, source and gate, the drain of said second N-channel MOS transistor being connected to the source of said first N-channel MOS transistor, the source of said P-channel MOS transistor being connected to a low-potential power source, the gate of said second N-channel MOS transistor being connected to the gates of said first P-channel and N-channel MOS transistors; and a third N-channel MOS transistor having a drain, source and gate, the drain of said third N-channel MOS transistor being connected to the source of said first N-channel MOS transistor, the source of said third N-channel MOS transistor being connected to said low-potential power source, the gate of said third N-channel MOS transistor being connected to said output of the circuit.
Claim 9
Dependent Claim
223 words
A semiconductor integrated circuit having a complementary metal oxide semiconductor (CMOS) inverter device, comprising: a CMOS inverter including a first P-channel MOS transistor having a drain, source and gate, and a first N-channel MOS transistor having a drain, source and gate, the source of said first P-channel MOS transistor being connected to a high-potential power source the drains of said first P- and N-channel MOS transistors being connected together and forming an output of said circuit, and the gates of said first P-channel and N-channel MOS transistors being mutually connected and supplied with an input signal; a second N-channel MOS transistor having a drain, source and gate, the drain of said second N-channel MOS transistor being connected to the source of said first N-channel MOS transistor, the source of said P-channel MOS transistor being connected to a low-potential power source, the gate of said second N-channel MOS transistor being connected to the gates of said first P-channel and N-channel MOS transistors; and a third N-channel MOS transistor having a drain, source and gate, the drain of said third N-channel MOS transistor being connected to the source of said first N-channel MOS transistor, the source of said third N-channel MOS transistor being connected to said low-potential power source, the gate of said third N-channel MOS transistor being connected to said output of the circuit.
Claim 10
Dependent Claim
28 words
A semiconductor integrated circuit as claimed in claim 7, wherein said third N-channel MOS transistor has a mutal transconductance higher than that of said second N-channel MOS transistor.
Claim 11
Dependent Claim
28 words
A semiconductor integrated circuit as claimed in claim 7, wherein said first N-channel MOS transistor has a mutal transconductance higher than that of said second N-channel MOS transistor.
Claim 12
Dependent Claim
20 words
A semiconductor integrated circuit as claimed in claim 7, wherein said second and third N-channel MOS transistors reduce ringing noise.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |