CMOS output buffer circuit

Claim 2

Complementary metal oxide semi-conductor (CMOS) type output buffer circuit comprising : an input terminal (1) for receiving an input signal ; a first voltage source for providing a first voltage ; a second voltage source for providing a second voltage ; a p channel output field effect transistor (FET) (71) having a gate ; an n channel output FET (72) having a gate, the p channel output FET and the n channel output FET being serially connected between the first and second voltage sources ; and at least a first time constant circuit (61 ; 62), connected between the input terminal (1) and one of the gates of the p and n channel output FETs (71 ; 72), for slowing down the voltage rise up or falling down of a signal appearing at said one of the gates of the p and n channel output FETs in response to the input signal ; the other one of the gates of the p and n channel output FETs (71 ; 72) being operatively connected to the input terminal (1).

Claim 3

A CMOS output buffer circuit according to claim 1, characterized in that it further comprises a second time constant circuit (61 ; 62), connected between the input terminal (1) and the other one of the gates of the p and n channel output FETs (71; 72).

Claim 4

CMOS output buffer circuit according to claim 1, characterized in that the first time constant circuit (61) is connected between the input terminal (1) and the gate of the p channel output FET (71).

Claim 5

CMOS output buffer circuit according to claim 1, characterized in that the first time constant circuit (62) is connected between the input terminal (1) and the gate of the n channel output FET (72).

Claim 6

CMOS output buffer circuit according to anyone of claims 1 to 4, characterized in that the first time constant circuit (61, 62) comprises a driver circuit for driving said one channel output FET and a resistor (R1, R2) connected in series between said driver circuit and one of the first and second voltage sources.

Claim 7

CMOS output buffer circuit according to claim 3, characterized in that the first time constant circuit (61) comprises a driver for driving the p channel output FET (71) and a resistor (R1) connected in series between the driver circuit and the second voltage source.

Claim 8

CMOS output buffer circuit according to claim 4, characterized in that the first time constant circuit (62) comprises a driver for driving the n channel output FET (72) and a resistor (R2) connected in series between the driver circuit and the first voltage source.

Claim 9

CMOS output buffer circuit according to claim 2, characterized in that the first time constant circuit (61) is connected to the gate of the p channel output FET (71) and comprises a driver circuit for driving the p channel output FET and a resistor (R1) connected in series between the driver circuit and the second voltage source ; and the second time constant circuit (62) is connected to the gate of the n channel output FET (72) and comprises a driver circuit for driving the n channel output FET and a resistor (R2) connected in series between the driver circuit and the first voltage source.

Claim 10

CMOS output buffer circuit according to claim 2, characterized in that the first time constant circuit (61) is connected to the gate of the p channel output FET (71) and comprises a driver circuit for driving the p channel output FET and an n channel FET (Q1) connected in series between the driver circuit and the second voltage source, the gate of said n channel FET (Q1) being connected to the first voltage source ; and the second time constant circuit (62) is connected to the gate of the n channel output FET (72) and comprises a driver circuit for driving the n channel output FET and a p channel output FET (Q2) connected in series between the driver circuit and the first voltage source, the gate of the p channel FET (Q2) being connected to the second voltage source.

Claim 11

CMOS output buffer circuit according to anyone of claims 5 to 9, characterized in that the driver circuit is an inverter composed of serially connected p channel FET and n channel FET.

Claim 12

CMOS output buffer circuit according to claim 10, characterized in that the p and n channel output FETs have a lower internal resistance than the one of the p and n channel FETs in the inverter.

Claim 13

Complementary metal oxide semi-conductor (CMOS) type output buffer circuit, characterized in that it comprises : an input terminal (1) for receiving control signals ; an output terminal (10) for providing output signals ; a first voltage source for providing a first voltage ; a second voltage source for providing a second voltage ; a p channel output field effect transistor (FET) (71) having a low internal resistance, the source of said p channel output FET being connected to the first voltage source ; an n channel output FET (72) having a low internal resistance, the drain of said n channel output FET (72) being connected to the drain of said p channel output FET (71) and to said output terminal (10), and the source of said n channel output FET (72) being connected to the second voltage source ; a first time constant circuit (61) connected to the gate of the p channel output FET (71), and comprising an inverter circuit (51) composed of serially connected p channel (FET) 511) and n channel FET (512), for driving the gate of said p channel output FET (71) ; and a resistor (R1) connected between the source of the n channel FET (512) and the second voltage source ; and       a second time constant circuit (62) connected to the gate of the n channel output FET (72), and comprising an inverter circuit (52) composed of serially connected p channel FET (521) and n channel FET (522), for driving said n channel output FET (72) ; and a resistor (R2) connected between the source of the p channel FET (521) and the first voltage source ; the gates of said p channel FETs (511, 521) and n channel FETs (512, 522) of said inverters being connected in common to the input terminal (1).

Claim 14

Complementary metal oxide semi-conductor (CMOS) type output buffer circuit, characterized in that it comprises : an input terminal (1) for receiving control signals ; an output terminal (10) for providing output signals ; a first voltage source for providing a first voltage ; a second voltage source for providing a second voltage ; a p channel output field effect transistor (FET) (71) having a low internal resistance, the source of said p channel output FET being connected to the first voltage source ; an n channel output FET (72) having a low internal resistance, the drain of said n channel output FET (72) being connected to the drain of said p channel output FET (71) and to said output terminal (10), and the source of said n channel output FET (72) being connected to the second voltage source ; a first time constant circuit (61) connected to the gate of the p channel output FET (71), and comprising an inverter circuit (51) composed of serially connected p channel (FET) 511) and n channel FET (512), for driving the gate of said p channel output FET (71) ; and a resistor (R1) connected between the source of the n channel FET (512) and the second voltage source ; and       a second time constant circuit (62) connected to the gate of the n channel output FET (72), and comprising an inverter circuit (52) composed of serially connected p channel FET (521) and n channel FET (522), for driving said n channel output FET (72) ; and a resistor (R2) connected between the source of the p channel FET (521) and the first voltage source ; the gates of said p channel FETs (511, 521) and n channel FETs (512, 522) of said inverters being connected in common to the input terminal (1).

Claim 15

Complementary metal oxide semi-conductor (CMOS) type output buffer circuit, characterized in that it comprises : an input terminal (1) for receiving control signals ; an output terminal (10) for providing output signals ; a first voltage source for providing a first voltage ; a second voltage source for providing a second voltage ; a p channel output field effect transistor (FET) (71) having a low internal resistance, the gate and source of which being connected respectively to the input terminal (1) and to the first voltage source ; an n channel output FET (72) having a low internal resistance, the drain of which being connected to the drain of said p channel output FET (71) and to the output terminal (10), and the source of the n channel output FET (72) being connected to the second voltage source ; a time constant circuit (62) connected to the gate of the n channel output FET (72), and comprising an inverter circuit (52) composed of serially connected p channel FET (521) and n channel FET (522), for driving the gate of said n channel output FET (72), and a resistor (R2) connected between the source of the p channel FET (521) and the first voltage source ; and a second inverter (2ʹ) having an input connected to the input terminal (1), and an output connected in common to the gates of the p channel FET (521) and n channel FET (522) of said inverter circuit (52).

Claim 16

Complementary metal oxide semi-conductor (CMOS) type output buffer circuit, characterized in that it comprises : an input terminal (1) for receiving control signals ; an output terminal (10) for providing output signals ; a first voltage source for providing a first voltage ; a second voltage source for providing a second voltage ; a p channel output field effect transistor (FET) (71) having a low internal resistance, the gate and source of which being connected respectively to the input terminal (1) and to the first voltage source ; an n channel output FET (72) having a low internal resistance, the drain of which being connected to the drain of said p channel output FET (71) and to the output terminal (10), and the source of the n channel output FET (72) being connected to the second voltage source ; a time constant circuit (62) connected to the gate of the n channel output FET (72), and comprising an inverter circuit (52) composed of serially connected p channel FET (521) and n channel FET (522), for driving the gate of said n channel output FET (72), and a resistor (R2) connected between the source of the p channel FET (521) and the first voltage source ; and a second inverter (2ʹ) having an input connected to the input terminal (1), and an output connected in common to the gates of the p channel FET (521) and n channel FET (522) of said inverter circuit (52).

Claim 17

Complementary metal oxide semi-conductor (CMOS) type output buffer circuit, characterized in that it comprises : an input terminal (1) for receiving control signals ; an output terminal (10) for providing output signals ; a first voltage source for providing a first voltage ; a second voltage source for providing a second voltage ; a p channel output field effect transistor (FET) (71) having a low internal resistance, the source of which being connected to said first voltage source ; an n channel output FET (72) having a low internal resistance, the drain of which being connected to the drain of the p channel output FET (71), and to the output terminal (10), and the source of the n channel output FET (72) being connected to the second voltage source ; a time constant circuit (61) connected to the gate of the n channel output FET (71), and comprising the inverter circuit (51) composed of serially connected p channel output FET (71), and a resistor (R1) connected between the source of the n channel FET (512) of the inverter circuit (51) and the second voltage source ; and a second inverter (2ʹ) having an input connected to the input terminal (1), and an output connected in common to the gates of the p channel FET (511) and n channel FET (512) of said inverter circuit (51).

Claim 18

Complementary metal oxide semi-conductor (CMOS) type output buffer circuit, characterized in that it comprises : an input terminal (1) for receiving control signals ; an output terminal (10) for providing output signals ; a first voltage source for providing a first voltage ; a second voltage source for providing a second voltage ; a p channel output field effect transistor (FET) (71) having a low internal resistance, the source of which being connected to said first voltage source ; an n channel output FET (72) having a low internal resistance, the drain of which being connected to the drain of the p channel output FET (71), and to the output terminal (10), and the source of the n channel output FET (72) being connected to the second voltage source ; a time constant circuit (61) connected to the gate of the n channel output FET (71), and comprising the inverter circuit (51) composed of serially connected p channel output FET (71), and a resistor (R1) connected between the source of the n channel FET (512) of the inverter circuit (51) and the second voltage source ; and a second inverter (2ʹ) having an input connected to the input terminal (1), and an output connected in common to the gates of the p channel FET (511) and n channel FET (512) of said inverter circuit (51).

Claim 19

CMOS output buffer circuit according to anyone of claims 12, 13 and 14, characterized in that said resistors (R1, R2) are respectively formed by the internal resistance of an n channel FET (Q1) and a p channel FET (Q2), the gates of which are respectively connected to one of the first or second voltage sources.