Drive circuit with limited signal transition rate for RFI reduction

Claim 2

A drive circuit, comprising: an output field-effect transistor for developing an output signal; an output terminal coupled to said output field-effect transistor; amplifier means responsive to a first level of an input signal supplied thereto for applying a turn-on bias to said output transistor; a first source of reference potential; switched current supply means coupled to said first source of reference potential and responsive to said first level of said input signal for supplying an operating current to said amplifier means for developing said turn-on bias; and power bypass means coupled to said amplifier means for diverting a portion of said operating current to a reference potential point during an initial portion of a turn-on interval, said bypass means being responsive to said turn-on bias during a second portion of said turn-on interval for reducing the magnitude of the current diverted from said amplifier means to zero as said output transistor turns on, so that said output signal at said otuput terminal exhibits a reduced rate of change with respect to changes of said input signal for reducing radio frequency interference.

Claim 3

A drive circuit as recited in claim 1 wherein said output transistor, said amplifier means, said switched current supply means and said power bypass means are formed in an integrated circuit, said output field-effect transistor having a drain electrode connected to an output bonding pad of said integrated circuit and further comprising an external load circuit coupled to said bonding pad, whereby rapid transitions of said input signal which tend to produce radio frequency interference are effectively isolated from said bonding pad and said external load circuit by said drive circuit so as to substantially confine said interference to said integrated circuit.

Claim 4

A drive circuit as recited in claim 1 wherein said switched current supply means and said bypass means comprises: a second source of reference potential; a first transistor having a source electrode connected to said second source of reference potential, a gate electrode connected to a signal input terminal of said amplifier means and a drain electrode connected to a power input terminal of said amplifier means; and a second transistor having a source electrode connected to said drain electrode of said first transistor, a drain electrode connected to said first source of reference potential and having a gate electrode connected to an output terminal of said amplifier means.

Claim 5

A drive circuit, comprising: a first P-channel transistor having a source electrode connected to a first potential supply source, a drain electrode connected to a first circuit node, and a gate electrode connected to an input terminal; a second P-channel transistor having a source electrode connected to said first circuit node, a drain electrode connected to a second circuit node and a gate electrode connected to said input terminal; a third N-channel transistor having a drain electrode connected to said second circuit node, a source electrode connected to a second potential supply source and a gate electrode connected to said input terminal; a fourth P-channel transistor having a gate electrode connected to said second circuit node, a source electrode connected to said first circuit node and a drain electrode connected to said second potential supply source; and a fifth N-channel transistor having a gate electrode connected to said second circuit node, a source electrode connected to said second potential suuply source and having a drain electrode connected to an output terminal; said second circuit node haivng a connection to a single low impedance point, said low impedance point beng said junction of said second P-channel transistor and said third N-channel transistor.

Claim 6

A drive circuit, comprising: a first P-channel transistor having a source electrode connected to a first potential supply source, a drain electrode connected to a first circuit node, and a gate electrode connected to an input terminal; a second P-channel transistor having a source electrode connected to said first circuit node, a drain electrode connected to a second circuit node and a gate electrode connected to said input terminal; a third N-channel transistor having a drain electrode connected to said second circuit node, a source electrode connected to a second potential supply source and a gate electrode connected to said input terminal; a fourth P-channel transistor having a gate electrode connected to said second circuit node, a source electrode connected to said first circuit node and a drain electrode connected to said second potential supply source; and a fifth N-channel transistor having a gate electrode connected to said second circuit node, a source electrode connected to said second potential suuply source and having a drain electrode connected to an output terminal; said second circuit node haivng a connection to a single low impedance point, said low impedance point beng said junction of said second P-channel transistor and said third N-channel transistor.

Claim 7

A drive circuit as recited in claim 4 wherein said first, second, third, fourth and fifth transistors are formed in an integrated circuit having an output bonding pad connected to said output terminal and further comprising an external load circuit coupled to said bonding pad, whereby rapid transistions of a control signal applied to said input terminal tending to produce radio frequency interference are isolated from said bonding pad and said external load circuit by said drive circuit thereby substantially confining said interference to said integrated circuit.

Claim 8

A drive circuit, comprising: a first P-channel transistor having a source electrode connected to a first potential suuply source, a drain electrode connected to a first circuit node, and a gate electrode connected to an input terminal; a second N-channel transistor having a drain electrode connected to said first circuit node, a source electrode connected to a second circuit node and a gate electrode connected to said input terminal; a third N-channel transistor having a drain electrode connected to said second circuit node, a source electrode connected to a second potential suuply source and a gate electrode connected to said input terminal; a fourth N-channel transistor having a drain electrode connected to said second circuit node, a gate electrode connected to said first circuit node and a drain electrode connected to said first potential supply source; and a fifth P-channel transistor having a source electrode connected to said first potential supply source, a gate electrode connected to said first circuit node and a drain electrode connected to an output terminal; said first circuit node having a connection to a single low impedance point, said low impedance point being said junction of said first P-channel transistor and said second N-channel transistor.

Claim 9

A drive circuit, comprising: a first P-channel transistor having a source electrode connected to a first potential suuply source, a drain electrode connected to a first circuit node, and a gate electrode connected to an input terminal; a second N-channel transistor having a drain electrode connected to said first circuit node, a source electrode connected to a second circuit node and a gate electrode connected to said input terminal; a third N-channel transistor having a drain electrode connected to said second circuit node, a source electrode connected to a second potential suuply source and a gate electrode connected to said input terminal; a fourth N-channel transistor having a drain electrode connected to said second circuit node, a gate electrode connected to said first circuit node and a drain electrode connected to said first potential supply source; and a fifth P-channel transistor having a source electrode connected to said first potential supply source, a gate electrode connected to said first circuit node and a drain electrode connected to an output terminal; said first circuit node having a connection to a single low impedance point, said low impedance point being said junction of said first P-channel transistor and said second N-channel transistor.

Claim 10

A drive circuit as recited in claim 6 wherein said first, second, third, fourth and fifth transistors are formed in an integrated circuit having an output bonding pad connected to said output terminal and further comprising an external load circuit coupled to said bonding pad, whereby rapid transistions of a control signal applied to said input terminal tending to produce radio frequency interference are effectively isolated from said bonding pad and said external load circuit by said drive circuit and thereby substantially confining said interference to said integrated circuit.

Claim 11

A drive circuit comprising, in combination: a first P-channel transistor having a conduction path connected between a first potential supply source and a first circuit node; a second P-channel transistor having a conduction path connected between said first circuit node and a second circuit node; a third N-channel transistor having a conduction path connected between said second circuit node and a third circuit node; a fourth N-channel transistor having a conduction path connected between said third circuit node and a second potential supply source; and a fifth P-channel transistor having a conduction path connected between said first circuit node and said second potential supply source and having a gate electrode connected to said second circuit node; a sixth N-channel transistor having a conduction path connected between said third circuit node and said first potential supply source and having a gate electrode connected to said second current node; and first circuit means for applying an input signal to the gate electrodes of said first, second, third and fourth transistors; and second circuit means coupled to an output terminal for deriving an output signal from said second circuit node, sid output signal at said output terminal exhibiting a reduced rate of change with respect to changes in said input signal for reducing radio frequency interference.

Claim 12

A drive circuit comprising, in combination: a first P-channel transistor having a conduction path connected between a first potential supply source and a first circuit node; a second P-channel transistor having a conduction path connected between said first circuit node and a second circuit node; a third N-channel transistor having a conduction path connected between said second circuit node and a third circuit node; a fourth N-channel transistor having a conduction path connected between said third circuit node and a second potential supply source; and a fifth P-channel transistor having a conduction path connected between said first circuit node and said second potential supply source and having a gate electrode connected to said second circuit node; a sixth N-channel transistor having a conduction path connected between said third circuit node and said first potential supply source and having a gate electrode connected to said second current node; and first circuit means for applying an input signal to the gate electrodes of said first, second, third and fourth transistors; and second circuit means coupled to an output terminal for deriving an output signal from said second circuit node, sid output signal at said output terminal exhibiting a reduced rate of change with respect to changes in said input signal for reducing radio frequency interference.

Claim 13

A drive circuit as recited in claim 8 wherein said circuit means comprises: a seventh N-channel transistor having a gate electrode connected to said second circuit node a source electrode connect to said second potential supply source and a drain electrode connected to an output terminal; an an eighth P-channel transistor having a gate electrode connected to said second circuit node, a drain electrode connected to said output terminal and a source electrode connected to said first potential supply source.

Claim 14

A drive circuit as recited in claim 9 wherein said transistors are formed in an integrated circuit having an output bonding pad connected to said output terminal and further comprising an external load coupled to said bonding pad whereby rapid transitions of said input signal which tend to produce radio frequency interference are effectively isolated from said bonding pad and said external load by said drive circuit thereby substantially confining said interference to said integrated circuit.