Method of manufacturing a semiconductor device including a trench capacitor

Claim 1

A method of manufacturing a semiconductor device including a trench capacitor, the method comprising the steps of: selectively etching a semiconductor substrate to form a groove therein; forming a conductive first layer on the sides and bottom of said groove and on said semiconductor substrate, said conductive first layer serving as a first plate electrode of said capacitor; forming an insulating second layer on said first layer and on said semiconductor substrate, said insulating second layer serving as a dielectric of said capacitor; forming a conductive third layer on said insulating second layer; patterning said third layer so as to remain at a position corresponding to that of said first plate electrode, in order to form a second plate electrode of said capacitor; forming an insulating fourth layer which covers said second plate electrode; forming a fifth layer on said fourth layer so as to fill said groove; etching said fifth layer so that it remains only in said groove; and forming an insulating sixth layer on said fifth layer.

Claim 2

A method of manufacturing a semiconductor device including a trench capacitor, the method comprising the steps of: selectively etching a semiconductor substrate to form a groove therein; forming a conductive first layer on the sides and bottom of said groove and on said semiconductor substrate, said conductive first layer serving as a first plate electrode of said capacitor; forming an insulating second layer on said first layer and on said semiconductor substrate, said insulating second layer serving as a dielectric of said capacitor; forming a conductive third layer on said insulating second layer; patterning said third layer so as to remain at a position corresponding to that of said first plate electrode, in order to form a second plate electrode of said capacitor; forming an insulating fourth layer which covers said second plate electrode; forming a fifth layer on said fourth layer so as to fill said groove; etching said fifth layer so that it remains only in said groove; and forming an insulating sixth layer on said fifth layer.

Claim 8

A method of manufacturing a semiconductor device having a memory cell comprising a trench capacitor and a MOS transistor, the method comprising the steps of: forming a first diffusion layer in a semiconductor substrate; selectively etching a semiconductor substrate to form a groove in a region of said substrate in which a capacitor is to be formed; forming a silicate glass layer containing impurities on the sides and bottom of; diffusing the impurities of the silicate glass layer into said semiconductor substrate along the sides and bottom of said groove, so as to form a first plate electrode of said capacitor; forming a dielectric layer, which serves as a dielectric of said capacitor, on said first plate electrode and said semiconductor substrate; forming a conductive layer including a polysilicon film, on said dielectric layer; patterning said conductive layer so as to remain in a region of said semiconductor substrate in which said capacitor is to be formed and so as not to extend over a region in which said MOS transistor is to be formed, in order to from a second plate electrode of said capacitor; forming an interlayer insulating film covering said second plate electrode; forming an embedded layer on said interlayer insulating film so as to fill said groove; etching said embedded layer so as to remain only in said groove; and forming an insulating film on said embedded layer.

Claim 9

A method of manufacturing a semiconductor device having a memory cell comprising a trench capacitor and a MOS transistor, the method comprising the steps of: forming a first diffusion layer in a semiconductor substrate; selectively etching a semiconductor substrate to form a groove in a region of said substrate in which a capacitor is to be formed; forming a silicate glass layer containing impurities on the sides and bottom of; diffusing the impurities of the silicate glass layer into said semiconductor substrate along the sides and bottom of said groove, so as to form a first plate electrode of said capacitor; forming a dielectric layer, which serves as a dielectric of said capacitor, on said first plate electrode and said semiconductor substrate; forming a conductive layer including a polysilicon film, on said dielectric layer; patterning said conductive layer so as to remain in a region of said semiconductor substrate in which said capacitor is to be formed and so as not to extend over a region in which said MOS transistor is to be formed, in order to from a second plate electrode of said capacitor; forming an interlayer insulating film covering said second plate electrode; forming an embedded layer on said interlayer insulating film so as to fill said groove; etching said embedded layer so as to remain only in said groove; and forming an insulating film on said embedded layer.