US4569701A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Technique for doping from a polysilicon transfer layer
Assignee: Nokia Bell Labs
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Filing: 1984-04-05
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Granted: 1986-02-11
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Expires: 2004-04-05
Abstract
Abstract For trench isolation technology or trench capacitor type memory cells, it is necessary to controllably dope the steep sidewalls of the trench. Implantation is ineffective and chemical doping sacrifices control. A thin transfer layer of polysilicon is deposited in the trench to conformally coat the sidewalls as well as the bottom of the trench and the top surface surrounding the trench. An impurity is implanted into the polysilicon at the bottom of the trench and around the top surface. Upon heating that impurity diffuses rapidly along the polysilicon layer inwardly and downwardly along the sidewalls. It then may be diffused into the substrate. The polysilicon layer may be etched away, or may be oxidized to SiO 2 and etched away, or left in place.
Inventors
- 👤 Kye H. Oh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:43
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/035
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
128 words
Method comprising: forming a polysilicon transfer layer overlying a semiconductor substrate, said transfer layer contacting said substrate at a first location, introducing impurities into said transfer layer selectively at a second location substantially removed from said first location in a direction normal with respect to the thickness of the transfer layer, said first and second locations being separated by a distance substantially greater than the thickness of the transfer layer, to produce in the transfer layer a relatively high impurity concentration at said second location and a relatively low impurity concentration at said first location, and heating said transfer layer at a temperature and for a time sufficient to transfer impurities from said second location to said first location in the transfer layer, and thereafter into said substrate.
Claim 2
Dependent Claim
128 words
Method comprising: forming a polysilicon transfer layer overlying a semiconductor substrate, said transfer layer contacting said substrate at a first location, introducing impurities into said transfer layer selectively at a second location substantially removed from said first location in a direction normal with respect to the thickness of the transfer layer, said first and second locations being separated by a distance substantially greater than the thickness of the transfer layer, to produce in the transfer layer a relatively high impurity concentration at said second location and a relatively low impurity concentration at said first location, and heating said transfer layer at a temperature and for a time sufficient to transfer impurities from said second location to said first location in the transfer layer, and thereafter into said substrate.
Claim 3
Dependent Claim
166 words
Method for introducing impurities into a semiconductor substrate comprising: forming at least one recession in the interior region of a planar single crystal semiconductor substrate, said recession including a sidewall portion and a bottom portion, said sidewall extending approximately vertically with respect to the plane of the substrate, depositing a transfer layer so as to substantially cover the sidewall portion of the recession, at least that portion of the surface of the substrate proximate the sidewall and/or the bottom portion of the recession, said transfer layer comprising a material in which the diffusion rate of said impurities is greater than in said substrate, implanting impurities into the portion of the transfer layer covering said surface portion and/or the bottom portion of the recession, and heating the substrate at a temperature and for a time sufficient to cause the implanted impurities to diffuse into at least significant parts of the transfer layer covering the sidewall portion and from that layer into the sidewall portion of the recession.
Claim 4
Dependent Claim
166 words
Method for introducing impurities into a semiconductor substrate comprising: forming at least one recession in the interior region of a planar single crystal semiconductor substrate, said recession including a sidewall portion and a bottom portion, said sidewall extending approximately vertically with respect to the plane of the substrate, depositing a transfer layer so as to substantially cover the sidewall portion of the recession, at least that portion of the surface of the substrate proximate the sidewall and/or the bottom portion of the recession, said transfer layer comprising a material in which the diffusion rate of said impurities is greater than in said substrate, implanting impurities into the portion of the transfer layer covering said surface portion and/or the bottom portion of the recession, and heating the substrate at a temperature and for a time sufficient to cause the implanted impurities to diffuse into at least significant parts of the transfer layer covering the sidewall portion and from that layer into the sidewall portion of the recession.
Claim 5
Dependent Claim
26 words
Method of claim 2 in which the diffusion rate of impurities in the transfer layer is at least five times the diffusion rate in the substrate.
Claim 6
Dependent Claim
14 words
Method of claim 2 in which the transfer layer is polysilicon or amorphous silicon.
Claim 7
Dependent Claim
13 words
Method of claim 2 in which the layer as deposited is substantially undoped.
Claim 8
Dependent Claim
16 words
Method of claim 2 in which the recession forms isolation between multiple devices in said substrate.
Claim 9
Dependent Claim
32 words
Method of claim 2 including the additional steps of forming a dielectric layer covering the substrate in the recession and depositing a conductive layer over the dielectric layer to form a capacitor.
Claim 10
Dependent Claim
24 words
Method of claim 7 in which the transfer layer is silicon and the dielectric layer is formed by oxidation of the silicon transfer layer.
Claim 11
Dependent Claim
15 words
Method of claim 2 in which the transfer layer is oxidized completely through its thickness.
Claim 12
Dependent Claim
12 words
Method of claim 9 in which the oxidized transfer layer is removed.
Claim 13
Dependent Claim
19 words
Method of claim 6 in which the recession is filled with a dielectric material after the sidewalls are doped.
Claim 14
Dependent Claim
11 words
Method of claim 7 in which the conductive layer is silicon.
Claim 15
Dependent Claim
13 words
Method of claim 12 in which the silicon layer substantially fills the recession.
Claim 16
Dependent Claim
20 words
Method of claim 2 in which a capping layer is formed over the transfer layer prior to the heating step.
References Cited (Backward Citations)
US4074304A
Cited
US4063967A
Cited
US4072545A
Cited
US4026733A
Cited
US4104086A
Cited
US4239559A
Cited
US4389255A
Cited
US4353086A
Cited
US4431460A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-10 | 1989-08-12 | 1990-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-10 | 1993-08-12 | 1994-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-10 | 1997-08-12 | 1998-02-11 | $7700.00 | Window Closed / Lapsed |