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Patent US5065212A successfully refreshed from Google Patents.
US5065212A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Toshiba Corp
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Filing: 1989-11-13
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Granted: 1991-11-12
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Expires: 2009-11-13
Abstract
Abstract There is a semiconductor device in which an n-type layer formed on a p + -type substrate is divided into first and second device forming regions by an isolation region and drive circuit devices and an output circuit device are respectively formed in these first and second device forming regions. The output circuit device is a conductivity modulated MOS transistor having the p + -type substrate as a drain and the second device forming regoin as a high resistance region whose conductivity is modulated.
Inventors
- 👤 Yu Ohata
- 👤 Tsuyoshi Kuramoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:28
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/411; H10D12/441; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W15/00; H10W15/01; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
309 words
An integrated semiconductor circuit having a drive circuit and a conductivity modulated MOS output transistor which has a high resistance layer whose conductivity can be modulated comprising: a P type semiconductor substrate having a main surface and a back surface; an N type semiconductor layer formed directly on said main surface of said P type semiconductor substrate and having an outer surface; an isolation region extending from said outer surface of the semiconductor layer to said P type semiconductor substrate to separate said semiconductor layer into first and second device forming regions; a drive circuit device formed in said first device forming region; at least one P type semiconductor region formed in the surface area of said second device forming region; an N type semiconductor region formed in each said P type semiconductor region; an insulation layer formed on at least a portion of each said P type semiconductor region which lies between said second device forming region and said N type semiconductor region; a gate electrode formed on said insulation layer; and a drain electrode formed on said back surface of said P type semiconductor substrate; wherein said gate electrode, said P type and N type semiconductor regions, said second device forming region, and said P type semiconductor substrate form a vertically disposed conductivity modulated MOS transistor through which a current flows from said P type semiconductor substrate to said N type semiconductor region through said N type semiconductor layer and said P type semiconductor region in said second device forming region, said MOS transistor having a high resistance layer whose conductivity can be modulated and which constitutes an output circuit, and wherein holes injected from said P type semiconductor substrate into said N type semiconductor layer through a PN junction formed therebetween serve to increase the conductivity of said high resistance layer during operation of the circuit.
Claim 2
Dependent Claim
309 words
An integrated semiconductor circuit having a drive circuit and a conductivity modulated MOS output transistor which has a high resistance layer whose conductivity can be modulated comprising: a P type semiconductor substrate having a main surface and a back surface; an N type semiconductor layer formed directly on said main surface of said P type semiconductor substrate and having an outer surface; an isolation region extending from said outer surface of the semiconductor layer to said P type semiconductor substrate to separate said semiconductor layer into first and second device forming regions; a drive circuit device formed in said first device forming region; at least one P type semiconductor region formed in the surface area of said second device forming region; an N type semiconductor region formed in each said P type semiconductor region; an insulation layer formed on at least a portion of each said P type semiconductor region which lies between said second device forming region and said N type semiconductor region; a gate electrode formed on said insulation layer; and a drain electrode formed on said back surface of said P type semiconductor substrate; wherein said gate electrode, said P type and N type semiconductor regions, said second device forming region, and said P type semiconductor substrate form a vertically disposed conductivity modulated MOS transistor through which a current flows from said P type semiconductor substrate to said N type semiconductor region through said N type semiconductor layer and said P type semiconductor region in said second device forming region, said MOS transistor having a high resistance layer whose conductivity can be modulated and which constitutes an output circuit, and wherein holes injected from said P type semiconductor substrate into said N type semiconductor layer through a PN junction formed therebetween serve to increase the conductivity of said high resistance layer during operation of the circuit.
Claim 3
Dependent Claim
18 words
A semiconductor circuit according to claim 1, wherein said isolation region is a P type third semiconductor region.
Claim 4
Dependent Claim
49 words
A semiconductor circuit according to claim 2, wherein said conductivity modulated MOS transistor further has an N type fourth semiconductor region which is formed between said second device forming region and said semiconductor substrate and which has an impurity concentration higher than that of said second device forming region.
Claim 5
Dependent Claim
53 words
A semiconductor circuit according to claim 3, wherein said drive circuit device includes a MOS transistor of one-channel type formed in said first device forming region, a P type fifth semiconductor region formed in said first device forming region, and a MOS transistor of an opposite-channel type formed in said fifth semiconductor region.
Claim 6
Dependent Claim
53 words
A semiconductor circuit according to claim 2, wherein said drive circuit device includes a MOS transistor of one-channel type formed in said first device forming region, a P type fifth semiconductor region formed in said first device forming region, and a MOS transistor of an opposite-channel type formed in said fifth semiconductor region.
Claim 7
Dependent Claim
15 words
A semiconductor circuit according to claim 1, wherein said isolation region is an insulation region.
Claim 8
Dependent Claim
49 words
A semiconductor circuit according to claim 6, wherein said conductivity modulated MOS transistor further has an N type fourth semiconductor region which is formed between said second device forming region and said semiconductor substrate and which has an impurity concentration higher than that of said second device forming region.
Claim 9
Dependent Claim
53 words
A semiconductor circuit according to claim 7, wherein said drive circuit device includes a MOS transistor of one-channel type formed in said first device forming region, a P type fifth semiconductor region formed in said first device forming region, and a MOS transistor of an opposite-channel type formed in said fifth semiconductor region.
Claim 10
Dependent Claim
53 words
A semiconductor circuit according to claim 6, wherein said drive circuit device includes a MOS transistor of one-channel type formed in said first device forming region, a P type fifth semiconductor region formed in said first device forming region, and a MOS transistor of an opposite-channel type formed in said fifth semiconductor region.
Claim 11
Dependent Claim
49 words
A semiconductor circuit according to claim 1, wherein said conductivity modulated MOS transistor further has an N type fourth semiconductor region which is formed between said second device forming region and said semiconductor substrate and which has an impurity concentration higher than that of said second device forming region.
Claim 12
Dependent Claim
53 words
A semiconductor circuit according to claim 10, wherein said drive circuit device includes a MOS transistor of one-channel type formed in said first device forming region, a P type fifth semiconductor region formed in said first device forming region, and a MOS transistor of an opposite-channel type formed in said fifth semiconductor region.
Claim 13
Dependent Claim
53 words
A semiconductor circuit according to claim 1, wherein said drive circuit device includes a MOS transistor of one-channel type formed in said first device forming region, a P type fifth semiconductor region formed in said first device forming region, and a MOS transistor of an opposite-channel type formed in said fifth semiconductor region.
Claim 14
Dependent Claim
31 words
A semiconductor circuit according to claim 1, wherein said second device forming region is a high resistance layer whose conductivity is modulated by the injection of carriers from said semiconductor substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-11-11 | 1995-05-13 | 1995-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-11 | 1999-05-13 | 1999-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-11 | 2003-05-13 | 2003-11-12 | $7700.00 | Window Closed / Lapsed |