US4879584A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with isolation between MOSFET and control circuit
Assignee: Toshiba Corp
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Filing: 1988-02-10
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Granted: 1989-11-07
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Expires: 2008-02-10
Abstract
Abstract A semiconductor device is provided which has a power insulated-gate MOS field effect transistor and a control semiconductor element formed in a common semiconductor substrate. A first area corresponding to a drain region of low resistance in the power MOS field effect transistor is different in resistivity than a second area corresponding to the control semiconductor element. The electrical characteristics of each element integrated in the devices is substantially equal to the same element in discrete form.
Inventors
- 👤 Yosuke Takagi
- 👤 Yu Ohata
- 👤 Koichi Kitahara
- 👤 Tsuyoshi Kuramoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:56
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/8311; H10D84/83138
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
126 words
A semiconductor device comprising: a power gate-insulated MOS field effect transistor having a drain region and a control circuit element formed on a common semiconductor substrate, said drain region having a high and a low resistance region, said high resistance region overlaying said low resistance region; a first area including at least a portion of said high resistance region of the drain region of the power gate-insulated MOS field effect transistor, said first area having a predetermined resistivity value; and a second area including at least a portion of the area in which said control circuit element is formed, said second area being disposed contiguous to said first area, said second area having a resistivity value less than said predetermined resistivity value of the first area.
Claim 2
Dependent Claim
126 words
A semiconductor device comprising: a power gate-insulated MOS field effect transistor having a drain region and a control circuit element formed on a common semiconductor substrate, said drain region having a high and a low resistance region, said high resistance region overlaying said low resistance region; a first area including at least a portion of said high resistance region of the drain region of the power gate-insulated MOS field effect transistor, said first area having a predetermined resistivity value; and a second area including at least a portion of the area in which said control circuit element is formed, said second area being disposed contiguous to said first area, said second area having a resistivity value less than said predetermined resistivity value of the first area.
Claim 3
Dependent Claim
59 words
A semiconductor device according to claim 1, wherein said power gate-insulated MOS field effect transistor has a source current taken from a first major surface side of said semiconductor substrate and has a drain current taken from a second major surface side of said semiconductor substrate, the second major surface side being disposed opposite said first major surface side.
Claim 4
Dependent Claim
33 words
A semiconductor device according to claim 1, wherein said power gate-insulated MOS field effect transistor has a source current and a drain current taken from a major surface side of said semiconductor substrate.
Claim 5
Dependent Claim
44 words
A semiconductive device according to claim 1, wherein said first area is formed by selectively etching at least a portion of the area that includes said power gate-insulated MOS field effect transistor, and epitaxially growing a layer in said etched portion of the area.
Claim 6
Dependent Claim
41 words
A semiconductor device according to claim 1, wherein said second area is formed by selectively etching at least a portion of the area occupied by said control circuit element, and epitaxially growing a layer in said etched portion of the area.
Claim 7
Dependent Claim
28 words
A semiconductor device according to claim 1, wherein one of said first and second areas is impurity-diffused for providing different resistivity values to the first and second areas.
Claim 8
Dependent Claim
23 words
A semiconductor device according to claim 1, wherein said first area is in contact with said low resistance region of said drain region.
Claim 9
Dependent Claim
24 words
A semiconductor device according to claim 1, wherein said first area is not in contact with said low resistance region of said drain region.
Claim 10
Dependent Claim
38 words
A semiconductor device according to claim 1, wherein the depth defined by a dimension substantially perpendicular to a major surface of the semiconductor substrate of the first area is substantially smaller than the depth of the second area.
Claim 11
Dependent Claim
34 words
A semiconductor device according to claim 1, wherein said first area has an impurity concentration gradient extending into the semiconductor substrate from a major surface thereof in a direction perpendicular to said major surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |