Semiconductor device having multi-layered wiring structure

Claim 2

A semiconductor device having a multi-layered structure, comprising: a pad applied with a predetermined potential; a plurality of circuits each having a predetermined function, said plurality of circuits including a first circuit and a second circuit, one of said first and second circuits being at least partially analog; a plurality of lines electrically connecting said pad to said circuits; an insulating interlayer between said pad and said plurality of circuits for electrically isolating said plurality of lines from each other; said plurality of lines including a first line electrically connecting a ground terminal of said first circuit to said pad and a second line, located under said first line, electrically connecting a ground terminal of said second circuit to said pad; and said insulating interlayer being sandwiched between said first line and said second line.

Claim 3

A semiconductor device according to claim 1, wherein at least one of said plurality of lines is parallelly superposed on another one of said lines on the semiconductor device.

Claim 4

A semiconductor device according to claim 1 or 2, wherein at least one of said plurality of lines crosses another one of said lines on the semiconductor device.

Claim 5

A semiconductor device according to claim 1, wherein said plurality of circuits further includes a third circuit; said plurality of lines further including a third line located under said second line connecting a ground terminal of said third circuit to said pad; and said insulating interlayer being sandwiched between said second line and said third line.

Claim 6

A semiconductor device according to claim 1, wherein said first circuit is a D/A converter wherein said ground terminal is an analog signal ground terminal, said second circuit is a D/A converter wherein said ground terminal is an analog signal ground terminal, and said plurality of circuits further includes a third D/A converter; said plurality of lines further including a third line connecting an analog signal ground terminal of said third D/A converter to said pad; and said insulating interlayer being sandwiched between said second line and said third line located under said second line.

Claim 7

A semiconductor device according to claim 5, wherein said plurality of lines further include a fourth line, being independent of said first, second and third lines, for connecting a digital signal ground terminal for each of said first, second and third D/A converters to said pad.

Claim 8

A semiconductor device according to claim 1, wherein said first circuit is a D/A converter wherein said ground terminal is an analog signal ground terminal, and said second circuit is a D/A converter wherein said ground terminal is an analog signal ground terminal; and said plurality of lines further including a third line connecting a digital signal ground terminal for each of said first and second D/A converters to a second pad, said third line being independent of said first and second lines.

Claim 9

A semiconductor device having a multi-layered structure, comprising: a first pad applied with a predetermined potential; a second pad applied with a predetermined potential; a plurality of circuits, said plurality of circuits including a first circuit, a second circuit, and a third circuit, one of said first, second and third circuits being at least partially analog; a plurality of lines electrically connecting each of said circuits to one of said first and second pads; an insulating interlayer between said first pad and said plurality of circuits and between said second pad and said plurality of circuits for electrically isolating said plurality of lines from each other; said plurality of lines including a first line for connecting said first circuit to said first pad, a second line for connecting said second circuit to said second pad, and a third line for connecting said third circuit to said first pad; said second line being under said first line and said third line being under said second line; and said insulating interlayer being sandwiched between said first line and second line, and said insulating interlayer being sandwiched between said second line and said third line.

Claim 10

A semiconductor device having a multi-layered structure, comprising: a first pad applied with a predetermined potential; a second pad applied with a predetermined potential; a plurality of circuits, said plurality of circuits including a first circuit, a second circuit, and a third circuit, one of said first, second and third circuits being at least partially analog; a plurality of lines electrically connecting each of said circuits to one of said first and second pads; an insulating interlayer between said first pad and said plurality of circuits and between said second pad and said plurality of circuits for electrically isolating said plurality of lines from each other; said plurality of lines including a first line for connecting said first circuit to said first pad, a second line for connecting said second circuit to said second pad, and a third line for connecting said third circuit to said first pad; said second line being under said first line and said third line being under said second line; and said insulating interlayer being sandwiched between said first line and second line, and said insulating interlayer being sandwiched between said second line and said third line.

Claim 11

A semiconductor device according to claim 8, wherein said first line is connected to a ground terminal of said first circuit, and said third line is connected to a ground terminal of said third circuit.

Claim 12

A semiconductor device according to claim 9, wherein said second line is connected to a ground terminal of said second circuit.

Claim 13

A semiconductor device according to claim 9, wherein said second line is connected to a signal terminal of said second circuit.

Claim 14

A semiconductor device having a multi-layered structure, comprising: a pad applied with a predetermined potential; a plurality of circuits each having a predetermined function, said plurality of circuits including a first circuit, a second circuit, a third circuit, and a fourth circuit, one of said first, second, third and fourth circuits being at least partially analog; a plurality of lines for electrically connecting said pad to said circuits; an insulating interlayer between said pad and said plurality of circuits for electrically isolating said plurality of lines from each other; said plurality of lines including a first line connecting a ground terminal of said first circuit to said pad, a second line connecting a signal terminal of said second circuit to a signal terminal of said fourth circuit, and a third line connecting a ground terminal of said third circuit to said pad; said second line being under said first line and said third line being under said second line; and said insulating interlayer being sandwiched between said first line and said second line, and said insulating layer being sandwiched between said second line and said third line; wherein said second line is electrostatically shielded by said first and second lines, each of said first and second lines having a ground potential.

Claim 15

A semiconductor device having a multi-layered structure, comprising: a pad applied with a predetermined potential; a plurality of circuits each having a predetermined function, said plurality of circuits including a first circuit, a second circuit, a third circuit, and a fourth circuit, one of said first, second, third and fourth circuits being at least partially analog; a plurality of lines for electrically connecting said pad to said circuits; an insulating interlayer between said pad and said plurality of circuits for electrically isolating said plurality of lines from each other; said plurality of lines including a first line connecting a ground terminal of said first circuit to said pad, a second line connecting a signal terminal of said second circuit to a signal terminal of said fourth circuit, and a third line connecting a ground terminal of said third circuit to said pad; said second line being under said first line and said third line being under said second line; and said insulating interlayer being sandwiched between said first line and said second line, and said insulating layer being sandwiched between said second line and said third line; wherein said second line is electrostatically shielded by said first and second lines, each of said first and second lines having a ground potential.