Patent US3360414A successfully refreshed from Google Patents.
EP0103362A2
Expired / Lapsed
EP
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Semiconductor device with power lines
Assignee: Fujitsu Ltd
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Filing: 1983-06-29
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Granted: —
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Expires: 2003-06-29
Abstract
Abstract A semiconductor device includes a power line (13) and sub power line (16) pair therein, both lines connected to the same power source. The power line is located on a layer under which a peripheral circuit region, such as input/output buffer circuits and output buffer circuits, is arranged in a semiconductor substrate. The sub power line is located above and electrically shorted with the power line. The electric shorts are formed, at least, at portions under which the output buffer circuits are located and connected to the power line.
Inventors
- 👤 Youzi Hino
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 20:19
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10D; H10D84/00; H10D84/01; H10D89/00; H10D89/10; H10W72/00; H10W72/90
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
133 words
A semiconductor device comprising: a semiconductor substrate; a logic circuit region arranged in the semiconductor substrate, said logic circuit region having a plurality of logic circuits; a peripheral circuit region arranged around said logic circuit region, said peripheral circuit region having a plurality of peripheral circuits, at least one of said peripheral circuits having an output buffer circuit; first and second power lines distributed, at least, along the peripheral circuit region; and a sub power line distributed on a layer different from a layer on which said first power line is distributed, in which electric shorts are formed between said first power line and said sub power line at portions under which one or more of said peripheral circuits including output buffer circuits therein are located and connected to the first power line.
Claim 2
Dependent Claim
133 words
A semiconductor device comprising: a semiconductor substrate; a logic circuit region arranged in the semiconductor substrate, said logic circuit region having a plurality of logic circuits; a peripheral circuit region arranged around said logic circuit region, said peripheral circuit region having a plurality of peripheral circuits, at least one of said peripheral circuits having an output buffer circuit; first and second power lines distributed, at least, along the peripheral circuit region; and a sub power line distributed on a layer different from a layer on which said first power line is distributed, in which electric shorts are formed between said first power line and said sub power line at portions under which one or more of said peripheral circuits including output buffer circuits therein are located and connected to the first power line.
Claim 3
Dependent Claim
34 words
A semiconductor device as set forth in claim 1, wherein the peripheral circuit region to be located under and connected with said electric shorts further includes an input buffer circuit composing said peripheral circuit.
Claim 4
Dependent Claim
24 words
A semiconductor device as set forth in claim 2, wherein said sub power line is electrically shorted via through-holes to said first power line.
Claim 5
Dependent Claim
25 words
A semiconductor device as set forth in claim 3, wherein said sub-power line is distributed in parallel with and right above said first power line.
Claim 6
Dependent Claim
53 words
A semiconductor device as set forth in claim 4, wherein both said first power line and said sub-power line are connected to either a first power source for supplying a first power source voltage or a second power source for supplying a second power source voltage higher than the first power source voltage.
Claim 7
Dependent Claim
58 words
A semiconductor device as set forth in claim 5, wherein the first power source is connected to the first power line, the second power source is connected to the second power line, the first power line is formed on a first layer, and the sub power line and the second power line are formed on a second layer.
Claim 8
Dependent Claim
41 words
A semiconductor device as set forth in claim 5, wherein the second power line is formed on a first layer, the first power line is formed on a second layer, and the sub power line is formed on a third layer.
Claim 9
Dependent Claim
26 words
A semiconductor device as set forth in claim 7, wherein said sub power line is wide enough to cover both the first and second power lines.
Claim 10
Dependent Claim
18 words
A semiconductor device as set forth in claim 1, wherein the first power line supplies a ground potential.
References Cited (Backward Citations)
No citation records indexed.
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