Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: an electronic circuit which includes an output section having at least a pair of output stage circuits, each one being separately supplied with a predetermined operation voltage from a voltage supply connection pad, said predetermined operation voltage being substantially of the same amplitude for each one of said at least a pair of output stage circuits; and wiring layer means formed on the main surface of a semiconductor substrate of said semiconductor integrated circuit device to separately supply said predetermined operation voltage to each one of said at least a pair of output stage circuits of said electronic circuit; wherein said wiring layer means is comprised of at least a first path and a second path respectively connected along opposite sides near the periphery of said substrate from said voltage supply connection pad which is located near one end on said substrate to individual ones of said at least a pair of output stage circuits of said electronic circuit output section which is located near an opposite end on said semiconductor substrate.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said electronic circuit performs a switching operation in response to input signals thereat.

Claim 4

A semiconductor integrated circuit device according to claim 2, further comprising: an internal circuit formed on the main surface of said semiconductor substrate and being powered by a predetermined operation voltage of a different amplitude than that for said at least a pair of output stage circuits; wherein said output stage circuits of said electronic circuit are comprised of means for providing respective external output signals to individual external output terminals associated therewith of said semiconductor integrated circuit device in response to input signals of said electronic circuit, and wherein at least one of said electronic circuit input signals is responsive to an output signal of said internal circuit.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein each one of said output stage circuits comprises an output transistor arrangement that generates said external output signal and which includes a pair of series-connected transistors having a size greater than that of other transistors in said internal circuit or elsewhere in said output stage circuit.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein each one of said series-connected transistors that generates said external output signal is a MOSFET.

Claim 7

A semiconductor integrated circuit device according to claim 5, wherein said electronic circuit further comprises a drive circuit for driving said pair of series connected MOSFETs, said drive circuit having an output portion including first and second pairs of series-connected bipolar transistors respectively coupled to the gate electrode of said MOSFETs.

Claim 8

A semiconductor integrated circuit device according to claim 6, wherein said drive circuit further comprises first and second CMOS circuits each having an output respectively coupled to drive said first and second pairs of series-connected bipolar transistors in a complementary manner, wherein said first CMOS circuit is arranged with said first pair of series-connected bipolar transistors to effect a NAND logic operation and said second CMOS circuit is arranged with said second pair of series-connected bipolar transistors to effect a NOR logic operation such that said series-connected pair of MOSFETs operates in a complementary switching manner.

Claim 9

A semiconductor integrated circuit device according to any one of claims 1 to 6, wherein said first path and said second path of said wiring layer means are formed on the main surface of a square semiconductor substrate adjacent the periphery along the four sides thereof.

Claim 10

A semiconductor integrated circuit device comprising: an electronic circuit which includes an output section having at least a pair of output stage circuits, each one being separately supplied with a first predetermined operation voltage from a voltage supply connection pad; a first wiring layer formed on the main surface of a semiconductor substrate of said semiconductor integrated circuit device to separately supply said first predetermined operation voltage to each one of said at least a pair of output stage circuits of said electronic circuit, wherein said first wiring layer is comprised of at least a first path and a second path respectively connected along opposite sides near the periphery of said substrate from said voltage supply connection pad which is located near the periphery of one side of a four-sided semiconductor substrate to said output section of said electronic circuit which is located near the periphery of an opposite side thereof; and a second wiring layer formed on the main surface of said semiconductor substrate which includes wirings respectively disposed in close proximity with respect to the individual wiring paths which supply said first predetermined operation voltage close to said first wiring layer; wherein said second wiring layer forms an AC loop.

Claim 11

A semiconductor integrated circuit device comprising: an electronic circuit which includes an output section having at least a pair of output stage circuits, each one being separately supplied with a first predetermined operation voltage from a voltage supply connection pad; a first wiring layer formed on the main surface of a semiconductor substrate of said semiconductor integrated circuit device to separately supply said first predetermined operation voltage to each one of said at least a pair of output stage circuits of said electronic circuit, wherein said first wiring layer is comprised of at least a first path and a second path respectively connected along opposite sides near the periphery of said substrate from said voltage supply connection pad which is located near the periphery of one side of a four-sided semiconductor substrate to said output section of said electronic circuit which is located near the periphery of an opposite side thereof; and a second wiring layer formed on the main surface of said semiconductor substrate which includes wirings respectively disposed in close proximity with respect to the individual wiring paths which supply said first predetermined operation voltage close to said first wiring layer; wherein said second wiring layer forms an AC loop.

Claim 12

A semiconductor integrated circuit device according to claim 9, wherein said electronic circuit performs a switching operation in response to input signals thereat.

Claim 13

A semiconductor integrated circuit device according to claim 10, further comprising: an internal circuit formed on the main surface of said semiconductor substrate and being powered by a second operating voltage, different than said first operating voltage; wherein said output stage circuits of said electronic circuit are comprised of means for providing respective external output signals to individual external output terminals associated therewith of said semiconductor integrated circuit device in response to input signals of said electronic circuit, and wherein at least one of said electronic circuit input signals is responsive to an output signal of said internal circuit.

Claim 14

A semiconductor integrated circuit device according to claim 11, wherein each one of said output stage circuits comprises an output transistor arrangement that generates said external output signal and which includes a pair of series-connected transistors having a size greater than that of other transistors in said internal circuit or elsewhere in said output stage circuit.

Claim 15

A semiconductor integrated circuit device according to claim 12, wherein each one of said series-connected transistors that generates said external output signal is a MOSFET.

Claim 16

A semiconductor integrated circuit device according to claim 13, wherein said electronic circuit further comprises a drive circuit for driving said pair of series-connected MOSFETs, said drive circuit having an output portion including respective pairs of series-connected bipolar transistors coupled to the gate electrode of said MOSFETs.

Claim 17

A semiconductor integrated circuit device according to claim 14, wherein said drive circuit further comprises a pair of CMOS circuits each having an output coupled to drive a respective pair of said series-connected bipolar transistors in a complementary manner, wherein a first of said CMOS circuits is arranged with a first of said pairs of series-connected bipolar transistors to effect a NAND logic operation and a second of said CMOS circuits is arranged with a second of said pairs of series-connected bipolar transistors to effect a NOR logic operation so that said series-connected pair of MOSFETs operate in a complementary switching manner.

Claim 18

A semiconductor integrated circuit device according to any one of said claims 9 to 14 wherein said first path and said second path of said first wiring layer are formed on the main surface of a square semiconductor substrate along the four sides thereof.

Claim 19

A semiconductor integrated circuit device according to claim 9, wherein part of said first wiring layer and part of said second wiring layer are at least solidly laminated.

Claim 20

A semiconductor integrated circuit device according to any one of claims 1 to 3, wherein said electronic circuit comprises four output stage circuits, each one being comprised of a bipolar transistor series-coupled with a MOSFET between a separate wiring path for supplying said predetermined operation voltage and reference potential, and which are disposed on said semiconductor substrate adjacent to external output pads; and wherein said wiring layer means comprises first and second pairs of conductor paths, said first pair being divided into first and second conductor paths and said second pair being divided into third and fourth conductor paths, wherein said first and third conductor paths and said second and fourth conductor paths are respectively in parallel and wherein said first and third conductor paths and said second and fourth conductor paths extend from a voltage supply connection pad located on one side of said substrate along respectively opposite sides of said substrate near the peripheries thereof to the respective output stage circuits.

Claim 21

A semiconductor integrated circuit device according to claim 18, wherein said wiring layer means further comprises magnetic shielding plate means for effecting mutual inductance isolation between said first and third conductor paths and between said second and fourth conductor paths, respectively.

Claim 22

A semiconductor integrate circuit device according to any one of claims 9 to 11, wherein said electronic circuit comprises four output stage circuits, each one being comprised of a bipolara transistor series-coupled with a MOSFET between a separate wiring path for supplying said predetermined operation voltage and reference potential, and which are disposed on said semiconductor substrate adjacent to external output pads; and wherein said first wiring layer comprises first and second pairs of conductor paths, said first pair being divided into first and second conductor paths and said second pair being divided into third and fourth conductor paths, wherein said first and third conductor paths and said second and fourth conductor paths are respectively in parallel and wherein said first and third conductor paths and said second and fourth conductor paths extend from a voltage supply connection pad located on one side of said substrate along respectively opposite sides of said substrate near the peripheries thereof to the respective output stage circuits.

Claim 23

A semiconductor integrated circuit device according to claim 20, wherein said second wiring layer further comprises magnetic shielding plate means for effecting mutual inductance isolation between said first and third conductor paths and between said second and fourth conductor paths, respectively.

Claim 24

A wiring arrangement for a semiconductor integrated circuit device formed on a main surface of a rectangular-shaped semiconductor substrate including an electronic circuit disposed near the periphery of one side of said semiconductor substrate and which includes an output section having at least a pair of output stage circuits for providing at least a pair of external output signals at corresponding external output pads, wherein each output stage circuit is separately supplied with a first predetermined operation voltage from a voltage supply connection pad, comprising: a voltage supply pad disposed near the periphery on an opposite side of said semiconductor substrate from where said electronic circuit is disposed for providing said predetermined operation voltage; and at least one wiring layer for separately providing said first predetermined operation voltage to each one of said output stage circuits when power is applied to said voltage supply pad, said wiring layer being divided into at least a pair of separated current paths extending along opposite regions and near the peripheries of the remaining two sides of said rectangular-shaped semiconductor substrate between said voltage supply pad and respective supply terminals of said output stage circuits thereby preventing any adverse changes in the predetermined operation voltage by effectively reducing the parasitic self-inductance of the conductor pairs and avoiding mutual inductance thereat.

Claim 25

A wiring arrangement for a semiconductor integrated circuit device formed on a main surface of a rectangular-shaped semiconductor substrate including an electronic circuit disposed near the periphery of one side of said semiconductor substrate and which includes an output section having at least a pair of output stage circuits for providing at least a pair of external output signals at corresponding external output pads, wherein each output stage circuit is separately supplied with a first predetermined operation voltage from a voltage supply connection pad, comprising: a voltage supply pad disposed near the periphery on an opposite side of said semiconductor substrate from where said electronic circuit is disposed for providing said predetermined operation voltage; and at least one wiring layer for separately providing said first predetermined operation voltage to each one of said output stage circuits when power is applied to said voltage supply pad, said wiring layer being divided into at least a pair of separated current paths extending along opposite regions and near the peripheries of the remaining two sides of said rectangular-shaped semiconductor substrate between said voltage supply pad and respective supply terminals of said output stage circuits thereby preventing any adverse changes in the predetermined operation voltage by effectively reducing the parasitic self-inductance of the conductor pairs and avoiding mutual inductance thereat.

Claim 26

A semiconductor integrated circuit device according to claim 22, wherein said electronic circuit includes four output stage circuits each one being supplied via a separate wiring current path of a first wiring layer which has two pairs of separate current path wirings extending along opposite regions and near the peripheries of said substrate from said voltage supply pad to supply terminals associated with said four output stage circuits.

Claim 27

A semiconductor integrated circuit device according to claim 22, said electronic circuit includes four output stage circuits and wherein said at least one wiring layer includes a first wiring layer and a second wiring layer, said first wiring layer including a first wiring path split into first and second conductor paths and a second wiring path split into third and fourth conductor paths, wherein said first and third conductor paths and said second and fourth conductor paths are respectively in parallel and wherein said first and third conductor paths and said second and fourth conductor paths extend from said power supply connection pad along respectively opposite sides of said substrate near the peripheries thereof to the respective supply terminals of said four output stage circuits.

Claim 28

A semiconductor integrated circuit device according to claim 24, further comprising a second wiring layer consisting of magnetic shielding plate means for effecting mutual inductance isolation between said first and third conductor paths and between said second and fourth conductor paths, respectively.

Claim 29

A semiconductor integrated circuit device according to claim 24, wherein said rectangular-shaped semiconductor substrate in a square semiconductor substrate.

Claim 30

A semiconductor integrated circuit device according to claim 25, wherein said rectangular-shaped semiconductor substrate is a square semiconductor substrate.

Claim 31

A semiconductor integrated circuit device according to claim 7, wherein said pair of series-connected MOSFETs are of the complementary channel type.

Claim 32

A semiconductor integrated circuit device according to claim 15, wherein said pair of series-connected MOSFETs are of the complementary channel type.

Claim 33

A semiconductor integrated circuit device according to claim 18, wherein each one of said four output stage circuits is comprised of an NPN bipolar transistor having a collector coupled to a wiring path for receiving said predetermined operation voltage, an emitter coupled via a diode junction to the drain of an N-channel MOSFET which has its source coupled to a reference ground potential, and wherein the base of said NPN bipolar transistor and the gate of said MOSFET are responsive to complementary signals in accordance with incoming signals of said electronic circuit.

Claim 34

A semiconductor integrated circuit device according to claim 20, wherein each one of said four output stage circuits is comprised of an NPN bipolar transistor having a collector coupled to a wiring path for receiving said predetermined operation voltage, an emitter coupled via a diode junction to the drain of an N-channel MOSFET which has its source coupled to a reference ground potential, and wherein the base of said NPN bipolar transistor and the gate of said MOSFET are responsive to complementary signals in accordance with incoming signals of said electronic circuit.

Claim 35

A semiconductor integrated circuit device according to claim 24, wherein each one of said four output stage circuits is comprised of an NPN bipolar transistor having a collector coupled to a wiring path for receiving said predetermined operation voltage, an emitter coupled via a diode junction to the drain of an N-channel MOSFET which has its source coupled to a reference ground potential, and wherein the base of said NPN bipolar transistor and the gate of said MOSFET are responsive to complementary signals in accordance with incoming signals of said electronic circuit.