Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first circuit node; an insulated gate field effect transistor coupled to said external terminal and said first circuit node for transmitting the input signal applied to said external terminal via a drain-source path thereof to said first circuit node, a gate of said first insulated gate field effect transistor being connected to an output terminal of a pulse generator circuit generating a switch signal; a resistance element inserted between said external terminal and said insulated gate field effect transistor; and an input circuit coupled to the first circuit node to receive said input signal transmitted to said first input circuit node via said drainsource path of said insulated gate field effect transistor, wherein said resistance element has a resistance value so set that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said resistance element reduces a breakdown current flowing through a semiconductor junction of said insulated gate field effect transistor to a level lower than a breakdown current level that causes breakdown of a gate insulating film of said insulated gate field effect transistor.

Claim 3

The semiconductor integrated circuit device as defined in claim 1, wherein said first circuit node is comprised of a gate electrode of an insulated gate field effect transistor which constitutes said input circuit.

Claim 4

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first circuit node; a second circuit node; a protective circuit coupled between said first circuit node and said external terminal to transmit the input signal supplied to said external terminal to said first circuit node, said protective circuit operating to restrict a maximum level of a voltage applied to said first circuit node to a predetermined level; a first resistance element having one end thereof connected to said first circuit node; a first insulated gate field effect transistor coupled to another end of said first resistance element and to said second circuit node, said first insulated gate field effect transistor supplying a signal supplied to said another end of said first resistance element via a drain-source path thereof to said second circuit node, a gate of said first insulated gate field effect transistor being connected to an output terminal of a pulse generator circuit generating a switch signal; an input circuit coupled to the second circuit node to receive said signal supplied to said second node via said drain-source path of said first insulated gate field effect transistor, wherein said first resistance element has a resistance value set so that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said first resistance element reduces a breakdown current flowing through a semiconductor junction of said first insulated gate field effect transistor to a level lower than a breakdown current level that causes breakdown of a gate insulating film of said first insulated gate field effect transistor, and further wherein the gate insulating film of said first insulated gate field effect transistor has a breakdown withstand voltage greater than the predetermined level to which said protective circuit restricts the maximum voltage at said first circuit node.

Claim 5

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first circuit node; a second circuit node; a protective circuit coupled between said first circuit node and said external terminal to transmit the input signal supplied to said external terminal to said first circuit node, said protective circuit operating to restrict a maximum level of a voltage applied to said first circuit node to a predetermined level; a first resistance element having one end thereof connected to said first circuit node; a first insulated gate field effect transistor coupled to another end of said first resistance element and to said second circuit node, said first insulated gate field effect transistor supplying a signal supplied to said another end of said first resistance element via a drain-source path thereof to said second circuit node, a gate of said first insulated gate field effect transistor being connected to an output terminal of a pulse generator circuit generating a switch signal; an input circuit coupled to the second circuit node to receive said signal supplied to said second node via said drain-source path of said first insulated gate field effect transistor, wherein said first resistance element has a resistance value set so that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said first resistance element reduces a breakdown current flowing through a semiconductor junction of said first insulated gate field effect transistor to a level lower than a breakdown current level that causes breakdown of a gate insulating film of said first insulated gate field effect transistor, and further wherein the gate insulating film of said first insulated gate field effect transistor has a breakdown withstand voltage greater than the predetermined level to which said protective circuit restricts the maximum voltage at said first circuit node.

Claim 6

The semiconductor integrated circuit device as defined in claim 3, wherein said second circuit node is comprised of a gate electrode of an insulated gate field effect transistor which constitutes said input circuit.

Claim 7

The semiconductor integrated circuit device as defined in claim 3, wherein said protective circuit is comprised of a second resistance element inserted between said external terminal and said first circuit node and a protective element substantially connected between said first circuit node and a reference potential point of said circuit which protective element has a breakdown voltage of a value lower than the breakdown voltage of the gate insulating film of said first insulated gate field effect transistor.

Claim 8

The semiconductor integrated circuit device as defined in claim 5, wherein said first resistance element is comprised of a resistor layer formed, via an insulating film, on a semiconductor substrate having formed on a surface thereof drain and source regions of said first insulated gate field effect transistor, and said second resistance element is comprised of a semiconductor region forming a p-n junction between said semiconductor region and said semiconductor substrate.

Claim 9

The semiconductor integrated circuit device as defined in claim 6, wherein the gate electrode of said first insulated gate field effect transistor and said first resistance element are formed by a polysilicon layer.

Claim 10

The semiconductor integrated circuit device as defined in claim 5, wherein said protective element is comprised of a second insulated gate field effect transistor having a drain thereof connected to said first conduit node and a source thereof connected to said reference potential point.

Claim 11

The semiconductor integrated circuit device as defined in claim 8, wherein said first insulated gate field effect transistor has a size smaller than that of said second insulated gate field effect transistor.

Claim 12

The semiconductor integrated circuit device as defined in claim 8, wherein said first insulated gate field effect transistor has a channel length shorter than that of said second gate insulated field effect transistor.

Claim 13

A semiconductor integrated circuit device including plural external terminals to which an input signal is supplied, plural first circuit nodes, plural insulated gate field effect transistors coupled to said external terminals and to said plural first circuit nodes for transmitting said input signal applied to each of said plural external terminals through drain-source paths to said plural first circuit nodes, and plural input circuits coupled to said plural first circuit nodes to receive said input signals transmitted to said plural first circuit nodes through said drain-source paths, wherein each gate of said insulated gate field effect transistors is connected to an output terminal of a pulse generator circuit generating switch signals, and further wherein said input signal is applied to each of said plural insulated gate field effect transistors via a protective circuit including means for limiting a voltage level below a predetermined level and a resistance element connected between said protective circuit and said insulated gate field effect transistors for limiting current applied to said insulated gate field effect transistors.

Claim 14

A semiconductor integrated circuit device including plural external terminals to which an input signal is supplied, plural first circuit nodes, plural insulated gate field effect transistors coupled to said external terminals and to said plural first circuit nodes for transmitting said input signal applied to each of said plural external terminals through drain-source paths to said plural first circuit nodes, and plural input circuits coupled to said plural first circuit nodes to receive said input signals transmitted to said plural first circuit nodes through said drain-source paths, wherein each gate of said insulated gate field effect transistors is connected to an output terminal of a pulse generator circuit generating switch signals, and further wherein said input signal is applied to each of said plural insulated gate field effect transistors via a protective circuit including means for limiting a voltage level below a predetermined level and a resistance element connected between said protective circuit and said insulated gate field effect transistors for limiting current applied to said insulated gate field effect transistors.

Claim 15

A semiconductor integrated circuit device comprising: an external terminal; first and second circuit nodes; a resistance element connected between said external terminal and said first circuit node; a protective element connected between said first circuit node and a reference potential point; an insulated gate field effect transistor having a drain-source path thereof connected between said first and second circuit nodes and receiving a switch signal at a gate thereof; and an input circuit coupled to said second circuit node to receive a signal supplied to said second circuit node through a drain-source path of said insulated gate field effect transistor, wherein said protective element has such a breakdown voltage as to restrict the voltage level appearing at said first circuit node when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal to a value lower than a breakdown voltage of the semiconductor junction of said insulated gate field effect transistor.

Claim 16

A semiconductor integrated circuit device comprising: an external terminal; first and second circuit nodes; a resistance element connected between said external terminal and said first circuit node; a protective element connected between said first circuit node and a reference potential point; an insulated gate field effect transistor having a drain-source path thereof connected between said first and second circuit nodes and receiving a switch signal at a gate thereof; and an input circuit coupled to said second circuit node to receive a signal supplied to said second circuit node through a drain-source path of said insulated gate field effect transistor, wherein said protective element has such a breakdown voltage as to restrict the voltage level appearing at said first circuit node when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal to a value lower than a breakdown voltage of the semiconductor junction of said insulated gate field effect transistor.

Claim 17

The semiconductor integrated circuit device as defined in claim 12 wherein said protective element is comprised of a diode having a cathode coupled to said first circuit node and an anode coupled to said reference potential point.

Claim 18

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first circuit node; a first insulated gate field effect transistor; second and third insulated gate field effect transistors coupled with their drain-source paths in series between said external terminal and a gate of said first insulated gate field effect transistor for transmitting the input signal applied to said external terminal via said drain-source paths thereof to said first circuit node; and a resistance element inserted between said external terminal and said second insulated gate field effect transistor, wherein said resistance element has a resistance value so set that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said resistance element reduces a breakdown current flowing through semiconductor junctions of said second and third insulated gate field effect transistors to a level lower than a breakdown current level that causes breakdown of gate insulating films of said second and third insulated gate field effect transistors.

Claim 19

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first circuit node; a first insulated gate field effect transistor; second and third insulated gate field effect transistors coupled with their drain-source paths in series between said external terminal and a gate of said first insulated gate field effect transistor for transmitting the input signal applied to said external terminal via said drain-source paths thereof to said first circuit node; and a resistance element inserted between said external terminal and said second insulated gate field effect transistor, wherein said resistance element has a resistance value so set that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said resistance element reduces a breakdown current flowing through semiconductor junctions of said second and third insulated gate field effect transistors to a level lower than a breakdown current level that causes breakdown of gate insulating films of said second and third insulated gate field effect transistors.

Claim 20

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first and a second circuit node; a first insulated gate field effect transistor; a protective circuit coupled between said first circuit node and said external terminal to transmit the input signal supplied to said external terminal to said first circuit node, said protective circuit operating to restrict a maximum level of a voltage applied to said first circuit node to a predetermined level; a first resistance element having one end thereof connected to said first circuit node; and second and third insulated gate field effect transistors coupled with their drain-source paths in series between another end of said first resistance element and a gate of said first insulated gate field effect transistor, said second and third insulated gate field effect transistors supplying a signal supplied to said another end of said first resistance element via a drain-source path thereof to said second circuit node, wherein said first resistance element has a resistance value set so that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said first resistance element reduces a breakdown current flowing through semiconductor junctions of said second and third insulated gate field effect transistors to a level lower than a breakdown current level that causes breakdown of gate insulating films of said second and third insulated gate field effect transistors, and further wherein the gate insulating films of said second and third insulated gate field effect transistors have a breakdown withstand voltage greater than the predetermined level to which said protective circuit restricts the maximum voltage at said first circuit node.

Claim 21

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first and a second circuit node; a first insulated gate field effect transistor; a protective circuit coupled between said first circuit node and said external terminal to transmit the input signal supplied to said external terminal to said first circuit node, said protective circuit operating to restrict a maximum level of a voltage applied to said first circuit node to a predetermined level; a first resistance element having one end thereof connected to said first circuit node; and second and third insulated gate field effect transistors coupled with their drain-source paths in series between another end of said first resistance element and a gate of said first insulated gate field effect transistor, said second and third insulated gate field effect transistors supplying a signal supplied to said another end of said first resistance element via a drain-source path thereof to said second circuit node, wherein said first resistance element has a resistance value set so that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said first resistance element reduces a breakdown current flowing through semiconductor junctions of said second and third insulated gate field effect transistors to a level lower than a breakdown current level that causes breakdown of gate insulating films of said second and third insulated gate field effect transistors, and further wherein the gate insulating films of said second and third insulated gate field effect transistors have a breakdown withstand voltage greater than the predetermined level to which said protective circuit restricts the maximum voltage at said first circuit node.

Claim 22

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first circuit node; a second circuit node; a protective circuit coupled between said first circuit node and said external terminal to transmit the input signal supplied to said external terminal to said first circuit node, said protective circuit operating to restrict a maximum level of a voltage applied to said first circuit node to a predetermined level; a first resistance element having one end thereof connected to said first circuit node; and a first insulated gate field effect transistor coupled to another end of said first resistance element and to said second circuit node, said first insulated gate field effect transistor supplying a signal supplied to said another end of said first resistance element via a drain-source path thereof to said second circuit node, wherein said first resistance element has a resistance value set so that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said first resistance element reduces a breakdown current flowing through a semiconductor junction of said first insulated gate field effect transistor to a level lower than a breakdown current level that causes breakdown of a gate insulating film of said first insulated gate field effect rransistor, wherein the gate insulating film of said first insulated gate field effect transistor has a breakdown withstand voltage greater than the predetermined level to which said protective circuit restricts the maximum voltage at said first circuit node, and further wherein said second circuit node is comprised of a gate electrode of an insulated gate field effect transistor for signal input.

Claim 23

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first circuit node; a second circuit node; a protective circuit coupled between said first circuit node and said external terminal to transmit the input signal supplied to said external terminal to said first circuit node, said protective circuit operating to restrict a maximum level of a voltage applied to said first circuit node to a predetermined level; a first resistance element having one end thereof connected to said first circuit node; and a first insulated gate field effect transistor coupled to another end of said first resistance element and to said second circuit node, said first insulated gate field effect transistor supplying a signal supplied to said another end of said first resistance element via a drain-source path thereof to said second circuit node, wherein said first resistance element has a resistance value set so that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said first resistance element reduces a breakdown current flowing through a semiconductor junction of said first insulated gate field effect transistor to a level lower than a breakdown current level that causes breakdown of a gate insulating film of said first insulated gate field effect rransistor, wherein the gate insulating film of said first insulated gate field effect transistor has a breakdown withstand voltage greater than the predetermined level to which said protective circuit restricts the maximum voltage at said first circuit node, and further wherein said second circuit node is comprised of a gate electrode of an insulated gate field effect transistor for signal input.

Claim 24

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first circuit node; a second circuit node; a protective circuit coupled between said first circuit node and said external terminal to transmit the input signal supplied to said external terminal to said first circuit node, said protective circuit operating to restrict a maximum level of a voltage applied to said first circuit node to a predetermined level; a first resistance element having one end thereof connected to said first circuit node; and a first insulated gate field effect transistor coupled to another end of said first resistance element and to said second circuit node, said first insulated gate field effect transistor supplying a signal supplied to said another end of said first resistance element via a drain-source path thereof to said second circuit node; wherein said first resistance element has a resistance value set so that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said first resistance element reduces a breakdown current flowing through a semiconductor junction of said first insulated gate field effect transistor to a level lower than a breakdown current level that causes breakdown of a gate insulating film of said first insulated gate field effect transistor, wherein the gate insulating film of said first insulated gate field effect transistor has a breakdown withstand voltage greater than the predetermined level to which said protective circuit restricts the maximum voltage at said first circuit node, and further wherein said protective circuit is comprised of a second resistance element inserted between said external terminal and said first circuit node and a protective element substantially connected between said first circuit node and a reference potential point of said circuit which protective element has a breakdown voltage of a value lower than the breakdown voltage of the gate insulating film of said first insulated gate field effect transistor.

Claim 25

A semiconductor integrated circuit device comprising: an external terminal to which an input signal is applied; a first circuit node; a second circuit node; a protective circuit coupled between said first circuit node and said external terminal to transmit the input signal supplied to said external terminal to said first circuit node, said protective circuit operating to restrict a maximum level of a voltage applied to said first circuit node to a predetermined level; a first resistance element having one end thereof connected to said first circuit node; and a first insulated gate field effect transistor coupled to another end of said first resistance element and to said second circuit node, said first insulated gate field effect transistor supplying a signal supplied to said another end of said first resistance element via a drain-source path thereof to said second circuit node; wherein said first resistance element has a resistance value set so that when an abnormal surge voltage having a voltage level greater than a normal predetermined input signal voltage level is applied to said external terminal, said first resistance element reduces a breakdown current flowing through a semiconductor junction of said first insulated gate field effect transistor to a level lower than a breakdown current level that causes breakdown of a gate insulating film of said first insulated gate field effect transistor, wherein the gate insulating film of said first insulated gate field effect transistor has a breakdown withstand voltage greater than the predetermined level to which said protective circuit restricts the maximum voltage at said first circuit node, and further wherein said protective circuit is comprised of a second resistance element inserted between said external terminal and said first circuit node and a protective element substantially connected between said first circuit node and a reference potential point of said circuit which protective element has a breakdown voltage of a value lower than the breakdown voltage of the gate insulating film of said first insulated gate field effect transistor.

Claim 26

The semiconductor integrated circuit device as defined in claim 17, wherein said first resistance element is comprised of a resistor layer formed, via an insulating film, on a semiconductor substrate having formed on a surface thereof drain and source regions of said first insulated gate field effect transistor, and said second resistance element is comprised of a semiconductor region forming a p-n function between said semiconductor region and said semiconductor substrate.

Claim 27

The semiconductor integrated circuit device as defined in claim 18, wherein the gate electrode of said first insulated gate field effect transistor and said first resistance element are formed by a polysilicon layer.

Claim 28

The semiconductor integrated circuit device as defined in claim 17, wherein said protective element is comprised of a second insulated gate field effect transistor having a drain thereof connected to said first circuit node and a source thereof connected to said reference potential point.

Claim 29

The semiconductor integrated circuit device as defined in claim 20, wherein said first insulated gate field effect transistor has a size smaller than that of said second insulated gate field effect transistor.

Claim 30

The semiconductor integrated circuit device as defined in claim 20, wherein said first insulated gate field effect transistor has a channel length shorter than that of said second gate insulated field effect transistor.