US4626889A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked differentially driven transmission line on integrated circuit
Assignee: Hitachi Ltd
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Filing: 1984-12-18
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Granted: 1986-12-02
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Expires: 2004-12-18
Abstract
Abstract A semiconductor integrated circuit structure including a semiconductor substrate having a large area adapted for a large scale integration, a circuit formed in the substrate for generating a pair of complementary signals, a pair of common potential level layers with an electrically insulating layer interposed therebetween, the common potential level layers being formed above and being electrically insulated from the substrate, and a pair of electric conductor pattern layers formed in the insulating layer for conducting the pair of complementary signals. The electric conductor pattern layers are arranged so as to be overlapped with each other in a direction substantially perpendicular to the large area substrate and so as to be substantially parallel with the large area substrate. The overall length of the electric conductor pattern layers is such that when an electric signal is conducted through an electric conductor in an IC having a length equal to the above-mentioned overall length, attenuation of the signal thereby is not negligible.
Inventors
- 👤 Masakazu Yamamoto
- 👤 Akira Masaki
- 👤 Ryotaro Kamikawai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:56
CPC Classifications
H; H10; H10W; H10W44/00; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
160 words
A semiconductor integrated circuit structure comprising: a semiconductor substrate having such a large area as being adapted for a large scale integration; circuit means formed in said semiconductor substrate for generating a pair of complementary signals in a phase-inverted relation with each other; a first common potential level layer formed above said substrate and electrically insulated from said substrate; a second common potential level layer formed above said first common potential level layer with an electrically insulating layer interposed therebetween; and at least one pair of electric conductor pattern layers formed in a spaced relation with each other in said insulating layer, said pair of conductor pattern layers being in electrical connection with said circuit means for conducting said pair of complementary signals to a desired point in said insulating layer and being arranged so as to be overlapped with each other in a direction substantially perpendicular to said substrate and so as to be substantially parallel with said substrate.
Claim 2
Dependent Claim
160 words
A semiconductor integrated circuit structure comprising: a semiconductor substrate having such a large area as being adapted for a large scale integration; circuit means formed in said semiconductor substrate for generating a pair of complementary signals in a phase-inverted relation with each other; a first common potential level layer formed above said substrate and electrically insulated from said substrate; a second common potential level layer formed above said first common potential level layer with an electrically insulating layer interposed therebetween; and at least one pair of electric conductor pattern layers formed in a spaced relation with each other in said insulating layer, said pair of conductor pattern layers being in electrical connection with said circuit means for conducting said pair of complementary signals to a desired point in said insulating layer and being arranged so as to be overlapped with each other in a direction substantially perpendicular to said substrate and so as to be substantially parallel with said substrate.
Claim 3
Dependent Claim
33 words
A structure according to claim 1, further comprising a pair of first termination resistances in electrical connection with said pair of conductor pattern layers, respectively, at said desired point in said insulating layer.
Claim 4
Dependent Claim
20 words
A structure according to claim 2, further comprising a second termination resistance interconnected between said pair of first termination resistances.
Claim 5
Dependent Claim
17 words
A structure according to claim 3, in which said first and second termination resistances are diffused resistances.
Claim 6
Dependent Claim
17 words
A structure according to claim 1, in which said insulating layer is made of a polyimide resin.
Claim 7
Dependent Claim
130 words
A structure according to claim 1, further comprising another pair of electric conductor pattern layers formed in a spaced relation with each other in said insulating layer and arranged so as to be overlapped with each other in a direction substantially perpendicular to said substrate and so as to be parallel with said substrate, said another pair of electric conductor pattern layers crossing the first-mentioned pair with one conductor pattern layer of one of said pair over one conductor pattern layer of the other pair so that part of said insulating layer is interposed between every adjacent two conductor pattern layers at the crossing, inter-level contact conductors being formed extending, perpendicularly to said substrate, between adjacent first two conductor pattern layers and between second adjacent two conductor pattern layers, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |