US5061982A
Expired / Lapsed
US
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VLSI triple-diffused polysilicon bipolar transistor structure
Assignee: Bipolar Integrated Technology Inc
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Filing: 1990-01-08
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Granted: 1991-10-29
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Expires: 2010-01-08
Abstract
Abstract A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop (32) and locally oxidizing a P-doped silicon substrate (21) to define a collector region, implanting an N-type collector (43) and diffusing the implants (40, 44). Device emitter, collector and base contact features (64, 66, 68) are photolithographically defined by two openings (54, 56) spaced lengthwise along the collector region. Low resistivity P- and N-type regions (74, 80) are implanted in the substrate in the openings and covered by local oxidation (86, 88). The collector region is preferably formed in a keyhole shape with a wide collector contact feature (66B) and adjoining region 80B and narrow base contact (68B) and emitter (64B) features and intervening region (74B). The substrate (22) is exposed in the emitter and contact features. A single polysilicon layer (94) is deposited, selectively doped and oxidized to form separate base, collector and emitter contacts (94) and a triple diffused NPN transistor (116, 92, 40).
Inventors
- 👤 Robert M. Drosd
- 👤 James M. Pickett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:16
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D10/00; H10D10/01; H10D10/051; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/13; H10D62/137; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; H10D84/00; H10D84/60; H10D84/641
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
333 words
A very large scale integrated circuit including a plurality of bipolar transistors, comprising: a lightly P-doped silicon substrate having a reference surface; a field oxide layer covering field portions of the reference surface and having a plurality of elongate openings each defining a collector region for each transistor, each opening having a predetermined width and length; a P-type channel stop in the substate beneath the field oxide layer and an N-type collector of a first depth in the substrate within each collector region, the channel stop and collector being spaced to form a P-N junction surrounding each collector region; each collector region having a first lengthwise end portion of a first width and a second, opposite end portion of a second width; each transistor including: an N-type collector contact region in the substrate in the first end portion of the collector region; a P-type base contact region in the substrate in the second end portion of the collector region; an emitter region centrally positioned within the collector region and including a P-type base in the substrate having a second depth less than the first depth and an N-type emitter having a third depth less than the second depth; a P-type low resistivity region, within the substrate subjacent the reference surface, connecting the base to the base contact region; an enhanced N-type low resistivity region, within the substrate immediately subjacent the reference surface, connecting the collector contact region to the P-type base, the low resistivity region forming an ohmic contact with the collector contact region and a P-N junction with the P-type base; and a second oxide layer formed in two separate, spaced apart portions selectively covering the substrate surface over each of the low resistivity regions so as to isolate the emitter from the collector and base contact regions; the emitter having a maximum length defined by the width of the opening in the field oxide and a maximum width defined by the spacing between the two portions of the second oxide layer.
Claim 2
Dependent Claim
333 words
A very large scale integrated circuit including a plurality of bipolar transistors, comprising: a lightly P-doped silicon substrate having a reference surface; a field oxide layer covering field portions of the reference surface and having a plurality of elongate openings each defining a collector region for each transistor, each opening having a predetermined width and length; a P-type channel stop in the substate beneath the field oxide layer and an N-type collector of a first depth in the substrate within each collector region, the channel stop and collector being spaced to form a P-N junction surrounding each collector region; each collector region having a first lengthwise end portion of a first width and a second, opposite end portion of a second width; each transistor including: an N-type collector contact region in the substrate in the first end portion of the collector region; a P-type base contact region in the substrate in the second end portion of the collector region; an emitter region centrally positioned within the collector region and including a P-type base in the substrate having a second depth less than the first depth and an N-type emitter having a third depth less than the second depth; a P-type low resistivity region, within the substrate subjacent the reference surface, connecting the base to the base contact region; an enhanced N-type low resistivity region, within the substrate immediately subjacent the reference surface, connecting the collector contact region to the P-type base, the low resistivity region forming an ohmic contact with the collector contact region and a P-N junction with the P-type base; and a second oxide layer formed in two separate, spaced apart portions selectively covering the substrate surface over each of the low resistivity regions so as to isolate the emitter from the collector and base contact regions; the emitter having a maximum length defined by the width of the opening in the field oxide and a maximum width defined by the spacing between the two portions of the second oxide layer.
Claim 3
Dependent Claim
33 words
A circuit according to claim 1 in which the collector region of each bipolar transistor has an average width of 1.4 um. or less and an average length of 10 um. or less.
Claim 4
Dependent Claim
87 words
A circuit according to claim 1 in which: the field oxide and second oxide layers each have a bird's beak margin surrounding and defining an edge of the emitter region; the P-type base is defined by a P-type implant extending a first predetermined distance beneath the bird's beak margin; and the emitter is defined by an N-type diffusion having a peak doping concentration at the reference surface in the substrate silicon and extending a second predetermined distance less than the first distance beneath the bird's beak margin.
Claim 5
Dependent Claim
32 words
A circuit according to claim 1 in which the emitter is dimensioned so that the transistor has a cutoff frequency f t of least 5 GHz at 50 uA of collector current.
Claim 6
Dependent Claim
20 words
A circuit according to claim 1 in which each transistor has a junction capacitance Cjc of 5 to 10 femtoFarads.
Claim 7
Dependent Claim
28 words
A circuit according to claim 1 in which the emitter has an average width of 1.0 um. or less and an average length of 1.4 um. or less.
Claim 8
Dependent Claim
69 words
A circuit according to claim 1 in which the first width of the first end portion of the collector region is greater than the second width of the second end portion thereof, the first end portion including a lengthwise portion of the N-type low resistivity region adjoining the collector contact region, and the emitter having a length defined by the second width of the opening in the field oxide.
Claim 9
Dependent Claim
32 words
A circuit according to claim 7 in which the collector region of each bipolar transistor has a physical second width of about 0.8 um. and a physical length of about 8.0 um.
Claim 10
Dependent Claim
39 words
A circuit according to claim 7 in which the second end portion, including the P-type base, P-type low-resistivity region and base contact region, is sized to an area not more than half the area of the first end portion.
Claim 11
Dependent Claim
32 words
A circuit according to claim 7 in which a portion of the N-type low resistivity region adjoining the collector contact region has a width about two times the length of the emitter.
Claim 12
Dependent Claim
33 words
A circuit according to claim 7 in which the collector region of each bipolar transistor has a physical first width of about 2.0 um. and a physical second width of about 0.8 um.
Claim 13
Dependent Claim
26 words
A circuit according to claim 7 in which the emitter has an electrical width of about 1.0 um. and an electrical length of about 1.2 um.
Claim 14
Dependent Claim
25 words
A circuit according to claim 7 in which the field oxide is formed by local oxidation and has a thickness of at least 11,000 Angstroms.
Claim 15
Dependent Claim
29 words
A circuit according to claim 7 in which the channel stop and collector are laterally diffused so as to form a shallow gradient P-N junction surrounding each collector region.
Claim 16
Dependent Claim
64 words
A circuit according to claim 7 in which the second end portion, including the P-type base, P-type low-resistivity region and base contact region, is sized to an area not more than half the area of the first end portion and a portion of the N-type low resistivity region adjoining the collector contact region has a width about two times the length of the emitter.
Claim 17
Dependent Claim
25 words
A circuit according to claim 1 in which the field oxide is formed by local oxidation and has a thickness of at least 11,000 Angstroms.
Claim 18
Dependent Claim
29 words
A circuit according to claim 1 in which the channel stop and collector are laterally diffused so as to form a shallow gradient P-N junction surrounding each collector region.
Claim 19
Dependent Claim
158 words
A bipolar transistor device structure adapted for fabrication in a very large scale integrated circuit, comprising: an N-type collector region of a first depth; an N-type collector contact region in a first end portion of the collector region; a P-type base contact region in a second end portion of the collector region; an emitter region centrally positioned within the collector region spaced between the base and collector contact regions and including a P-type base having a second depth less than the first depth and an N-type emitter positioned within the P-type base and having a third depth less than the second depth; a P-type low resistivity region laterally connecting the base to the base contact region; and an enhanced N-type low resistivity region substantially within the second depth connecting the collector contact region to the P-type base, the low resistivity region forming an ohmic contact with the collector contact region and a P-N junction with the P-type base.
Claim 20
Dependent Claim
158 words
A bipolar transistor device structure adapted for fabrication in a very large scale integrated circuit, comprising: an N-type collector region of a first depth; an N-type collector contact region in a first end portion of the collector region; a P-type base contact region in a second end portion of the collector region; an emitter region centrally positioned within the collector region spaced between the base and collector contact regions and including a P-type base having a second depth less than the first depth and an N-type emitter positioned within the P-type base and having a third depth less than the second depth; a P-type low resistivity region laterally connecting the base to the base contact region; and an enhanced N-type low resistivity region substantially within the second depth connecting the collector contact region to the P-type base, the low resistivity region forming an ohmic contact with the collector contact region and a P-N junction with the P-type base.
Claim 21
Dependent Claim
32 words
A bipolar transistor device structure according to claim 18 in which the collector region has an average width of 1.4 μm. or less and an average length of 10 μm. or less.
Claim 22
Dependent Claim
34 words
A bipolar transistor device structure according to claim 18 in which the emitter is dimensioned so that the transistor has a cutoff frequency ft of least 5 GHz at 50 uA of collector current.
Claim 23
Dependent Claim
31 words
A bipolar transistor device structure according to claim 18 in which the emitter has an average width of 1.0 μm. or less and an average length of 1.4 μm. or less.
Claim 24
Dependent Claim
19 words
A bipolar transistor device structure according to claim 18 having a junction capacitance Cjc o f5 to 10 femtoFarads.
Claim 25
Dependent Claim
39 words
A bipolar transistor device structure according to claim 18 having an oxide layer formed in two separate, spaced apart portions selectively covering each of the low resistivity regions to isolate the emitter from the collector and base contact regions.
Claim 26
Dependent Claim
232 words
A bipolar transistor device structure adapted for fabrication in a very large scale integrated circuit, comprising: an N-type collector region of a first depth; an N-type collector contact region of a first width in a first end portion of the collector region; a P-type base contact region of a second width in a second end portion of the collector region; an emitter region of substantially said second width centrally positioned within the collector region between the base and collector contact regions and including a P-type base having a second depth less than the first depth and an N-type emitter having a third depth less than the second depth; a P-type low resistivity region of substantially said second width laterally connecting the base to the base contact region; and an enhanced N-type low resistivity region of substantially aid first width laterally connecting the collector contact region to the P-type base; the transistor having a parasitic collector resistance determined by the width of the enhanced N-type low resistivity region, and a parasitic collector-to-base capacitance determined by the width of an interface of the collector region with the P-type base, the P-type base contact region, and the p-type low resistivity region, and the first width being sized to a dimension greater than the second width such that the value of the parasitic collector resistance is decreased without increasing the value of the parasitic collector-to-base capacitance.
Claim 27
Dependent Claim
232 words
A bipolar transistor device structure adapted for fabrication in a very large scale integrated circuit, comprising: an N-type collector region of a first depth; an N-type collector contact region of a first width in a first end portion of the collector region; a P-type base contact region of a second width in a second end portion of the collector region; an emitter region of substantially said second width centrally positioned within the collector region between the base and collector contact regions and including a P-type base having a second depth less than the first depth and an N-type emitter having a third depth less than the second depth; a P-type low resistivity region of substantially said second width laterally connecting the base to the base contact region; and an enhanced N-type low resistivity region of substantially aid first width laterally connecting the collector contact region to the P-type base; the transistor having a parasitic collector resistance determined by the width of the enhanced N-type low resistivity region, and a parasitic collector-to-base capacitance determined by the width of an interface of the collector region with the P-type base, the P-type base contact region, and the p-type low resistivity region, and the first width being sized to a dimension greater than the second width such that the value of the parasitic collector resistance is decreased without increasing the value of the parasitic collector-to-base capacitance.
Claim 28
Dependent Claim
32 words
A bipolar transistor device structure according to claim 24 in which the collector region of each bipolar transistor has a width of about 0.8 μm. and a length of about 8.0 μm.
Claim 29
Dependent Claim
41 words
A bipolar transistor device structure according to claim 24 in which the second end portion, including the P-type base, low-resistivity region and base contact region, is sized to an area not more than half the area of the first end portion.
Claim 30
Dependent Claim
35 words
A bipolar transistor device structure according to claim 24 in which a portion of the N-type low resistivity region adjoining the collector contact region has a width about two times the length of the emitter.
Claim 31
Dependent Claim
31 words
A bipolar transistor device structure according to claim 24 in which the first width of the collector region is about 2.0 μm. and the second width thereof is about 0.8 μm.
Claim 32
Dependent Claim
29 words
A bipolar transistor device structure according to claim 24 in which the emitter has an electrical width of about 1.0 μm. and an electrical length of about 1.2 μm.
Claim 33
Dependent Claim
66 words
A bipolar transistor device structure according to claim 24 in which the second end portion,. including the P-type base, low-resistivity region and base contact region, is sized to an area not more than half the area of the first end portion, and a portion of the N-type low resistivity region adjoining the collector contact region has a width about two times the length of the emitter.
Claim 34
Dependent Claim
39 words
A bipolar transistor device structure according to claim 24 having an oxide layer formed in two separate, spaced apart portions selectively covering each of the low resistivity regions to isolate the emitter from the collector and base contact regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-28 | 1995-04-29 | 1995-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-28 | 1999-04-29 | 1999-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-28 | 2003-04-29 | 2003-10-29 | $7700.00 | Window Closed / Lapsed |