Semiconductor device and its manufacturing method

Abstract

Abstract PURPOSE:To reduce the size of an element having super self-alignment transistor structure by forming each side of an emitter region at approximately equal distances from a boundary between an element region and an isolation region in the periphery of the element region. CONSTITUTION:A field oxide film 11 for isolation, an element region, is shaped to the main surface of a semiconductor substrate 1. A P<+> type external base region 13a is formed while being self-aligned with an N<-> type epitaxial layer 4 shaped in the element region. a P-type intrinsic base region 13b, which is self-aligned and continues to the region 13a, and an N-type emitter region 19 are formed. The region 19 is shaped separated only by approximately equal distances from several side of a boundary between the region 13a and the film 11 at that time. Consequently, only one mask may be used for forming the element region, the region 13a and the region 19. Accordingly, the allowance of mask alignment need not be prepared, thus reducing the size of an element for a transistor only by a section corresponding to the unnecessity of the allow ance of mask alignment, then accelerating the speed of operation of the transis tor.

Inventors

• 👤 Toshihiko Takakura
• 👤 俊彦 高倉
• 👤 Hirotaka Nishizawa
• 👤 裕孝 西沢
• 👤 Akio Anzai
• 👤 安斎　昭夫

Bibliographic Details