Amorphous silicon thin film transistor with a depletion gate

Claim 1

A process for fabricating an amorphous silicon thin film transistor, comprising the steps of: (a) forming an accumulation gate on a substrate; (b) depositing a bottom insulating layer on the substrate and the accumulation gate; (c) depositing a hydrogenated amorphous silicon (a-Si) channel layer on the bottom insulating layer; (d) depositing a top insulating layer on the amorphous silicon channel layer; (e) partially removing said top insulating layer so as to expose separate source and drain regions of said channel layer; (f) depositing a doped a-Si film of a first conductivity type as the ohmic-contact layer of the transistor; (g) partially removing the doped a-Si film to expose an intermediate portion of the top insulator between the separate source and drain regions of the channel layer, so as to form separate source and drain ohmic contact layers overlying, respectively, said source and drain regions of said channel layer, and removing remaining parts of the doped a-Si film and the undoped a-Si layer outside the defined active region to expose portions of the bottom insulating layer, so as to define the active region of the transistor; (h) partially removing the bottom insulator to expose a contact hole of the accumulation gate; (i) depositing a metal film over said source and drain ohmic contact layers, said top insulation layer and the accumulation contact hole; (j) partially removing the metal film so as to form a depletion gate electrode on said intermediate portion of said top insulating layer, source and drain electrodes on said source and drain ohmic contact layers, and the interconnection of the accumulation gate electrode.