Electro-optical display panel with control transistors and method for making it

Claim 2

An electro-optical display panel with control transistors comprising: a first strip and a second strip (1, 1') which are parallel and which enclose an electro-optical material (CX); the first strip (1) being provided on its surface (10), in contact with the electro-optical material (CX), with a matrix of pixels (PX11 to PX22) arranged in lines and columns, line control electrodes (LG1, LG2) at a rate of one electrode associated with each line of pixels of said matrix and placed parallel to each line pixels, and control transistors (T11 to T22) at a rate of one transistor per pixel (PX11 to PX22) coupling the pixel to said line control electrodes; the second strip (1') being provided, on its surface (10') in contact with the electro-optical material (CX), with at least one electrode (F); characterized in that each transistor comprised: a gate (GR) placed on the surface (10) and associated with a line control electrode (LG); a first layer (2) of insulating material covering the entire surface (10) with the line control electrodes (LG) and the gates (GR); an element (3) made of amorphous semi-conductive material overlapping the gate (GR); a source (SO) placed on this element (3) made of amorphous semi-conductive material and extending from one edge of the gate towards a pixel; a drain (DR) placed on said element (3) made of amorphous semi-conductor material and extending from another edge of the gate towards a column electrode; a second layer of insulant material (6) covering the entire panel on which the following elements are placed: at least one pixel (PX); a first connection element (CSP) crossing the second insulant layer (6) and connecting the source (SO) to the pixel (PX); at least one column control electrode (CL); a second connecting element (CDC) crossing the second insulant layer (6) and connecting the drain (DR) to said column control electrode; a light barrier (EC) placed above the gate.

Claim 3

A panel according to claim 1 characterized in that the light barrier (EC) is made of a metallic material.

Claim 4

A panel according to claim 1 characterized in that it comprises, on the surface (10) of the first strip (1), duplicated portions of column electrodes (Col 1, Col 2) interrupted in the vicinity of each control transistor and connected by connection elements (CX4, CX5), crossing the first and second insulant layers (2 and 6), to a column control electrode (CL).

Claim 5

A panel according to claim 1 characterized in that it comprises, on the second layer of insulant material (6) duplicated portions of line electrodes (LG1) interrupted in the vicinity of each transistor and connected by connection elements (CX3), crossing the first and second insulant layers (2 and 6) to a line electrode (LG).

Claim 6

A panel according to claim 1 characterized in that each pixel (PX) is located between the first and second layers of insulant material (2, 6).

Claim 7

A panel according to claim 5 characterized in that it comprises connection elements (CSP) crossing the second insulant layer (6) and connecting the source (SO) with a pixel (PX).

Claim 8

A panel according to claim 5 characterized in that each pixel has a connection directly connecting the pixel (PX) to a source (SO).

Claim 9

A panel according to claim 1 characterized in that each element (3) made of amorphous semi-conducting material is slightly compensated in boron to reduce its photoconductivity.

Claim 10

A panel according to claim 1 characterized in that: the element (3) made of amorphous semi-conducting material covers a part of the gate (GR) so as to be completely shielded from the light that reaches the substrate; the source (SO) comprises at least one indentation crosswise with respect to the gate (GR) and the element (3) made of semi-conducting material; the drain (DR) also has at least one indentation parallel to the indentation of the source (SO); the light barrier (EC) is placed above the gate and the element (3) made of semi-conductive material (3), thus overlapping the source and drain indentations.

Claim 11

A panel according to claim 2 characterized in that the drain (DR) comprises at least two indentations framing an indentation of the source (SO).

Claim 12

A panel according to claim 1 characterized in that the pixel (PX) comprises an indentation which extends over the line electrode that controls it.

Claim 13

A method for making a liquid crystal display panel according to claim 1 characterized in that it comprises the following steps: a first step for making on a surface (10) of first strip (1) of line control electrodes (LG), gates (GR) connected to these line control electrodes (LG) and portions of column electrodes (Col 1, Col 2) that do not cut the line electrodes (LG). (b) a second step for the successive making of a first insulant layer (2), a layer of an amorphous semi-conducting material (3), a layer of a doped semi-conducting material (4); (c) a third step of making two etchings, in the layer of amorphous semi-conductive material (3), of elements that each overlap a gate (GR) and, in the layer of doped semi-conducting material, of a source (SO) and a drain (DR) leaving an unoccupied space above the gate and extending, as for the source (SO), towards the location of a pixel and, as for the drain (DR), towards the location of a column electrode; (d) a fourth step for the making of a second passivation insulant layer (6); (e) a fifth step for the etching of cavities (CX1, CX2) for the connection of contacts crossing the second insulant layer (6) at the location of the sources and drains, and of cavities (CX3, CX4, CX5) for the connection of contacts crossing the first layer and second layer of insulant (2, 6) at the location of the line and column electrodes; (f) a sixth step for the depositing of a layer of a conductive material; (g) a seventh step for the etching of pixels (PX) in this conductive layer; (h) an eighth step for the depositing of a metallic layer over the layers on the surface; (i) a ninth step for the etching in this metallic layer: of column control electrodes passing through the cavities for the connection of contacts (CX4, CX5), enabling them to be connected to portions of column electrodes (Col 1, Col 2); portions of line electrodes passing through the cavities for the connection of contacts (CX3) enabling them to be connected to line control electrodes (LG); connection elements connecting, firstly, a source (SO) to column electrode and, secondly, a drain to a pixel; light barriers (EC) shielding the amorphous semiconducting material on top of the gate from an incident light; (j) a tenth step for finishing a panel comprising the following operations: the depositing of a fixing layer; the positioning of thickness shims; the making of the counter-strip with a transparent counter-electrode covered with a fixing strip; placing of a liquid crystal.

Claim 14

A method according to claim 12 characterized in that the second step is completed by making a layer of metal (5) and in that, during the third step, this layer is also etched to make the source (SO) and drain (DR) contacts.

Claim 15

A method according to claim 12 characterized in that the first step comprises a step for depositing a metallic layer on a surface (10) of a substrate 1 followed by a stage for the etching by photolithography of the line control electrodes (LG), gates (GR) and column electrode portions (Col 1, Col 2).

Claim 16

A method according to claim 12 characterized in that the insulant is Si 3 N 3 .

Claim 17

A method according to claim 12 characterized in that the semi-conducting material is silicon.

Claim 18

A method according to claim 12 characterized in that the second step is performed by a plasma-assisted heat decomposition method or by sputtering.

Claim 19

A method according to claim 12 characterized in that the second step comprises the making of a metallic layer (5) on the layer of doped semi-conducting material (4).

Claim 20

A method according to claim 18 characterized in that the third step comprises: a first stage for the etching of the metallic layer (5) and the layer of doped semi-conducting material (4); a second stage for the etching of the layer of amorphous semi-conducting material (3).

Claim 21

A method according to claim 12 characterized in that the third, the fifth and the seventh steps are performed by photolithography.

Claim 22

A method according to claim 12 characterized in that in the sequence of step the sixth and seventh steps precede the fifth step.

Claim 23

A method according to claim 12 characterized in that the sixth and seventh steps precede the fourth step.

Claim 24

A method according to claim 22 characterized in that the seventh step provides for the etching of the connection elements (CSP) of the pixels with the sources and in that the ninth step then does not provide for the making of the connection elements of the pixels with the sources.

Claim 25

A method according to claim 12 characterized in that the sixth and the seventh steps are performed after the ninth step.