Shared inverter outputs delay system

Claim 1

A logic level propagation delay system having an input and an output, said system comprising: a plurality of multiple output signal level inverters, including first and second multiple output signal level inverters, each said multiple output signal level inverter having a first input and first and second outputs such that each said multiple output signal level inverter, if electrically energized, has its first and second outputs at one logic state voltage level if input signals of a magnitude range less than a first threshold value are applied to its first input and at an opposite logic state voltage level if such input signals are of a magnitude ragne exceeding a second threshold value with a change in magnitude in such input signals between said magnitude ranges leading to a corresponding change in logic state voltage levels at said first and second outputs thereof but which occurs only after first and second switching delays following such a change in magnitude in said input signals, respectively; a set of intermediate signal level inverters having at least a first intermediate signal level inverter therein, each of said intermediate signal level inverters having a first input and an output such that each said intermediate signal level inverter, if electrically energized, has its output at one logic state voltage level if input signals of a magnitude range less than a third threshold value are applied to its first input and at an opposite logic state voltage value if such input signals are of a magnitude range exceeding a fourth threshold value with a change in magnitude in such input signals between said magnitude ranges leading to a corresponding change in logic state voltage levels at said output thereof but which occurs only after an intermediate switching delay following such a change in magnitude in said input signals; and an inverter sequence comprising said first and second multiple output signal level inverters and said first intermediate signal level inverter, said first multiple output signal level inverter first input serving as said system input with any of said outputs thereof electrically connected to said second multiple output signal level inverter first input being so connected solely through said first intermediate signal level inverter, said first multiple output signal level inverter first output being electrically connected to said first intermediate signal level inverter first input which is free of any direct connection from any of said outputs of said second multiple output signal level inverter, said first intermediate signal level inverter output being electrically connected to said second multiple output signal level inverter first input and said first multiple output signal level inverter second output and said second multiple output signal level inverter second output each being electrically connected to said system output.